MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing
1f34390 @ 2012-03-10 10:50:55
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| testbed.vhd | implemented ethernet RX packet and TX clock in testbed | 2012-03-06 20:48:33 |