MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing 1f34390 @ 2012-03-10 10:50:55
..
eth_pack.hex implemented ethernet RX busmaster -> packet reception working 2012-03-03 23:42:55
eth_pack.nib implemented ethernet RX busmaster -> packet reception working 2012-03-03 23:42:55