mips_sys

MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

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Stefan Schuermans Stefan Schuermans decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete 11c7383 @ 2012-02-05 17:32:53
constraints start of MIPS core: begin of decoder and ALU 2012-01-23 22:06:18
doc MIPS ISA spec 2012-01-24 21:41:27
mips decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete 2012-02-05 17:32:53
.gitignore start of MIPS core: begin of decoder and ALU 2012-01-23 22:06:18
mips_sys.xise compare unit, initial PC ideas 2012-01-25 18:56:29