implement correctly writing to register file (feaa63d) - mips_sys · BlinkenArea

mips/core.vhd

@@ -27,10 +27,17 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL s_alu:    t_alu;
     SIGNAL s_imm:    t_imm;
     
+    SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
+
     SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_res: std_logic_vector(31 DOWNTO 0);
 
+    SIGNAL s_reg_wr_no:   std_logic_vector( 4 DOWNTO 0);
+    SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_reg_wr_en:   std_logic;
+
     COMPONENT e_mips_decoder IS
         PORT (
             i_instr:  IN  std_logic_vector(31 DOWNTO 0);
@@ -94,12 +101,12 @@ BEGIN
             rst         => rst,
             clk         => clk,
             i_rd_a_no   => s_reg_s,
-            o_rd_a_data => s_op1,
+            o_rd_a_data => s_val_s,
             i_rd_b_no   => s_reg_t,
-            o_rd_b_data => s_op2,
-            i_wr_no     => s_reg_d,
-            i_wr_data   => s_res,
-            i_wr_en     => '1'
+            o_rd_b_data => s_val_t,
+            i_wr_no     => s_reg_wr_no,
+            i_wr_data   => s_reg_wr_data,
+            i_wr_en     => s_reg_wr_en
         );
 
     alu: e_mips_alu
@@ -113,12 +120,59 @@ BEGIN
     p_dummy_fetch: PROCESS(rst, clk)
     BEGIN
         IF rst = '1' THEN
-            r_instr <= X"00000000";
+            r_instr <= (OTHERS => '0');
         ELSIF rising_edge(clk) THEN
-            r_instr <= std_logic_vector(unsigned(r_instr) + to_unsigned(1, 32));
+            r_instr <= std_logic_vector(unsigned(r_instr) +
+                                        to_unsigned(1, 32));
         END IF;
     END PROCESS p_dummy_fetch;
 
+    p_alu_in: PROCESS(s_op, s_imm, s_val_s, s_val_t, s_imm_a, s_imm_16)
+    BEGIN
+        s_op1 <= (OTHERS => '0');
+        s_op2 <= (OTHERS => '0');
+        IF s_op = op_alu THEN
+            CASE s_imm IS
+                WHEN imm_none =>
+                    s_op1 <= s_val_s;
+                    s_op2 <= s_val_t;
+                WHEN imm_a =>
+                    s_op1(4 DOWNTO 0) <= s_imm_a;
+                    s_op2 <= s_val_t;
+                WHEN imm_16se =>
+                    s_op1 <= s_val_s;
+                    s_op2(15 DOWNTO 0) <= s_imm_16;
+                    IF (s_imm_16(15) = '1') THEN
+                        s_op2(31 DOWNTO 16) <= (OTHERS => '1');
+                    END IF;
+                WHEN imm_16ze =>
+                    s_op1 <= s_val_s;
+                    s_op2(15 DOWNTO 0) <= s_imm_16;
+                WHEN OTHERS => NULL;
+            END CASE;
+        END IF;
+    END PROCESS p_alu_in;
+
+    p_reg_wr: PROCESS(s_op, s_imm, s_reg_t, s_reg_d)
+    BEGIN
+        s_reg_wr_no   <= (OTHERS => '0');
+        s_reg_wr_data <= (OTHERS => '0');
+        s_reg_wr_en   <= '0';
+        IF s_op = op_alu THEN
+            CASE s_imm IS
+                WHEN imm_none | imm_a =>
+                    s_reg_wr_no   <= s_reg_d;
+                    s_reg_wr_data <= s_res;
+                    s_reg_wr_en   <= '1';
+                WHEN imm_16se | imm_16ze =>
+                    s_reg_wr_no   <= s_reg_t;
+                    s_reg_wr_data <= s_res;
+                    s_reg_wr_en   <= '1';
+                WHEN OTHERS => NULL;
+            END CASE;
+        END IF;
+    END PROCESS p_reg_wr;
+
     o_res <= s_res;
 
 END ARCHITECTURE a_mips_core;


...	...	@@ -27,10 +27,17 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
27	27	SIGNAL s_alu: t_alu;
28	28	SIGNAL s_imm: t_imm;
29	29
	30	+ SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
	31	+ SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
	32	+
30	33	SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
31	34	SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
32	35	SIGNAL s_res: std_logic_vector(31 DOWNTO 0);
33	36
	37	+ SIGNAL s_reg_wr_no: std_logic_vector( 4 DOWNTO 0);
	38	+ SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);
	39	+ SIGNAL s_reg_wr_en: std_logic;
	40	+
34	41	COMPONENT e_mips_decoder IS
35	42	PORT (
36	43	i_instr: IN std_logic_vector(31 DOWNTO 0);
...	...	@@ -94,12 +101,12 @@ BEGIN
94	101	rst => rst,
95	102	clk => clk,
96	103	i_rd_a_no => s_reg_s,
97		- o_rd_a_data => s_op1,
	104	+ o_rd_a_data => s_val_s,
98	105	i_rd_b_no => s_reg_t,
99		- o_rd_b_data => s_op2,
100		- i_wr_no => s_reg_d,
101		- i_wr_data => s_res,
102		- i_wr_en => '1'
	106	+ o_rd_b_data => s_val_t,
	107	+ i_wr_no => s_reg_wr_no,
	108	+ i_wr_data => s_reg_wr_data,
	109	+ i_wr_en => s_reg_wr_en
103	110	);
104	111
105	112	alu: e_mips_alu
...	...	@@ -113,12 +120,59 @@ BEGIN
113	120	p_dummy_fetch: PROCESS(rst, clk)
114	121	BEGIN
115	122	IF rst = '1' THEN
116		- r_instr <= X"00000000";
	123	+ r_instr <= (OTHERS => '0');
117	124	ELSIF rising_edge(clk) THEN
118		- r_instr <= std_logic_vector(unsigned(r_instr) + to_unsigned(1, 32));
	125	+ r_instr <= std_logic_vector(unsigned(r_instr) +
	126	+ to_unsigned(1, 32));
119	127	END IF;
120	128	END PROCESS p_dummy_fetch;
121	129
	130	+ p_alu_in: PROCESS(s_op, s_imm, s_val_s, s_val_t, s_imm_a, s_imm_16)
	131	+ BEGIN
	132	+ s_op1 <= (OTHERS => '0');
	133	+ s_op2 <= (OTHERS => '0');
	134	+ IF s_op = op_alu THEN
	135	+ CASE s_imm IS
	136	+ WHEN imm_none =>
	137	+ s_op1 <= s_val_s;
	138	+ s_op2 <= s_val_t;
	139	+ WHEN imm_a =>
	140	+ s_op1(4 DOWNTO 0) <= s_imm_a;
	141	+ s_op2 <= s_val_t;
	142	+ WHEN imm_16se =>
	143	+ s_op1 <= s_val_s;
	144	+ s_op2(15 DOWNTO 0) <= s_imm_16;
	145	+ IF (s_imm_16(15) = '1') THEN
	146	+ s_op2(31 DOWNTO 16) <= (OTHERS => '1');
	147	+ END IF;
	148	+ WHEN imm_16ze =>
	149	+ s_op1 <= s_val_s;
	150	+ s_op2(15 DOWNTO 0) <= s_imm_16;
	151	+ WHEN OTHERS => NULL;
	152	+ END CASE;
	153	+ END IF;
	154	+ END PROCESS p_alu_in;
	155	+
	156	+ p_reg_wr: PROCESS(s_op, s_imm, s_reg_t, s_reg_d)
	157	+ BEGIN
	158	+ s_reg_wr_no <= (OTHERS => '0');
	159	+ s_reg_wr_data <= (OTHERS => '0');
	160	+ s_reg_wr_en <= '0';
	161	+ IF s_op = op_alu THEN
	162	+ CASE s_imm IS
	163	+ WHEN imm_none \| imm_a =>
	164	+ s_reg_wr_no <= s_reg_d;
	165	+ s_reg_wr_data <= s_res;
	166	+ s_reg_wr_en <= '1';
	167	+ WHEN imm_16se \| imm_16ze =>
	168	+ s_reg_wr_no <= s_reg_t;
	169	+ s_reg_wr_data <= s_res;
	170	+ s_reg_wr_en <= '1';
	171	+ WHEN OTHERS => NULL;
	172	+ END CASE;
	173	+ END IF;
	174	+ END PROCESS p_reg_wr;
	175	+
122	176	o_res <= s_res;
123	177
124	178	END ARCHITECTURE a_mips_core;
125	179