mips/core.vhd (feaa63d) - mips_sys · BlinkenArea

core.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;

ENTITY e_mips_core IS
    PORT (
        rst:   IN  std_logic;
        clk:   IN  std_logic;
        o_res: OUT std_logic_vector(31 DOWNTO 0)
    );
END ENTITY e_mips_core;

ARCHITECTURE a_mips_core OF e_mips_core IS

SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);

SIGNAL s_reg_s:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL s_reg_t:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL s_reg_d:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL s_imm_a:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL s_imm_16: std_logic_vector(15 DOWNTO 0);
    SIGNAL s_imm_26: std_logic_vector(25 DOWNTO 0);
    SIGNAL s_op:     t_op;
    SIGNAL s_link:   t_link;
    SIGNAL s_cmp:    t_cmp;
    SIGNAL s_alu:    t_alu;
    SIGNAL s_imm:    t_imm;
    
    SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);

SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_res: std_logic_vector(31 DOWNTO 0);

SIGNAL s_reg_wr_no:   std_logic_vector( 4 DOWNTO 0);
    SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_reg_wr_en:   std_logic;

COMPONENT e_mips_decoder IS
        PORT (
            i_instr:  IN  std_logic_vector(31 DOWNTO 0);
            o_reg_s:  OUT std_logic_vector( 4 DOWNTO 0);
            o_reg_t:  OUT std_logic_vector( 4 DOWNTO 0);
            o_reg_d:  OUT std_logic_vector( 4 DOWNTO 0);
            o_imm_a:  OUT std_logic_vector( 4 DOWNTO 0);
            o_imm_16: OUT std_logic_vector(15 DOWNTO 0);
            o_imm_26: OUT std_logic_vector(25 DOWNTO 0);
            o_op:     OUT t_op;
            o_link:   OUT t_link;
            o_cmp:    OUT t_cmp;
            o_alu:    OUT t_alu;
            o_imm:    OUT t_imm
        );
    END COMPONENT e_mips_decoder;

COMPONENT e_mips_regs IS
        PORT (
            rst:         IN  std_logic;
            clk:         IN  std_logic;
            i_rd_a_no:   IN  std_logic_vector( 4 DOWNTO 0);
            o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
            i_rd_b_no:   IN  std_logic_vector( 4 DOWNTO 0);
            o_rd_b_data: OUT std_logic_vector(31 DOWNTO 0);
            i_wr_no:     IN  std_logic_vector( 4 DOWNTO 0);
            i_wr_data:   IN  std_logic_vector(31 DOWNTO 0);
            i_wr_en:     IN  std_logic
        );
    END COMPONENT e_mips_regs;

COMPONENT e_mips_alu IS
        PORT (
            i_alu: IN  t_alu;
            i_op1: IN  std_logic_vector(31 DOWNTO 0);
            i_op2: IN  std_logic_vector(31 DOWNTO 0);
            o_res: OUT std_logic_vector(31 DOWNTO 0)
        );
    END COMPONENT e_mips_alu;

BEGIN

decoder: e_mips_decoder
        PORT MAP (
            i_instr  => r_instr,
            o_reg_s  => s_reg_s,
            o_reg_t  => s_reg_t,
            o_reg_d  => s_reg_d,
            o_imm_a  => s_imm_a,
            o_imm_16 => s_imm_16,
            o_imm_26 => s_imm_26,
            o_op     => s_op,
            o_link   => s_link,
            o_cmp    => s_cmp,
            o_alu    => s_alu,
            o_imm    => s_imm
        );

regs: e_mips_regs
        PORT MAP (
            rst         => rst,
            clk         => clk,
            i_rd_a_no   => s_reg_s,
            o_rd_a_data => s_val_s,
            i_rd_b_no   => s_reg_t,
            o_rd_b_data => s_val_t,
            i_wr_no     => s_reg_wr_no,
            i_wr_data   => s_reg_wr_data,
            i_wr_en     => s_reg_wr_en
        );

alu: e_mips_alu
        PORT MAP (
            i_alu => s_alu,
            i_op1 => s_op1,
            i_op2 => s_op2,
            o_res => s_res
        );

p_dummy_fetch: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_instr <= (OTHERS => '0');
        ELSIF rising_edge(clk) THEN
            r_instr <= std_logic_vector(unsigned(r_instr) +
                                        to_unsigned(1, 32));
        END IF;
    END PROCESS p_dummy_fetch;

p_alu_in: PROCESS(s_op, s_imm, s_val_s, s_val_t, s_imm_a, s_imm_16)
    BEGIN
        s_op1 <= (OTHERS => '0');
        s_op2 <= (OTHERS => '0');
        IF s_op = op_alu THEN
            CASE s_imm IS
                WHEN imm_none =>
                    s_op1 <= s_val_s;
                    s_op2 <= s_val_t;
                WHEN imm_a =>
                    s_op1(4 DOWNTO 0) <= s_imm_a;
                    s_op2 <= s_val_t;
                WHEN imm_16se =>
                    s_op1 <= s_val_s;
                    s_op2(15 DOWNTO 0) <= s_imm_16;
                    IF (s_imm_16(15) = '1') THEN
                        s_op2(31 DOWNTO 16) <= (OTHERS => '1');
                    END IF;
                WHEN imm_16ze =>
                    s_op1 <= s_val_s;
                    s_op2(15 DOWNTO 0) <= s_imm_16;
                WHEN OTHERS => NULL;
            END CASE;
        END IF;
    END PROCESS p_alu_in;

p_reg_wr: PROCESS(s_op, s_imm, s_reg_t, s_reg_d)
    BEGIN
        s_reg_wr_no   <= (OTHERS => '0');
        s_reg_wr_data <= (OTHERS => '0');
        s_reg_wr_en   <= '0';
        IF s_op = op_alu THEN
            CASE s_imm IS
                WHEN imm_none | imm_a =>
                    s_reg_wr_no   <= s_reg_d;
                    s_reg_wr_data <= s_res;
                    s_reg_wr_en   <= '1';
                WHEN imm_16se | imm_16ze =>
                    s_reg_wr_no   <= s_reg_t;
                    s_reg_wr_data <= s_res;
                    s_reg_wr_en   <= '1';
                WHEN OTHERS => NULL;
            END CASE;
        END IF;
    END PROCESS p_reg_wr;

o_res <= s_res;

END ARCHITECTURE a_mips_core;

mips_sys

implement correctly writing to register file