mips_sys

rename src/dest to more general name
Parent 0a29d2e
Stefan Schuermans

Stefan Schuermans commited on 2012-01-24 21:00:05
Showing 2 changed files, with 29 additions and 29 deletions.

mips/core.vhd
View file @ cbae278
... ... 
@@ -15,9 +15,9 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
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     SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);
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-    SIGNAL s_src_s:  std_logic_vector( 4 DOWNTO 0);
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-    SIGNAL s_src_t:  std_logic_vector( 4 DOWNTO 0);
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-    SIGNAL s_dest:   std_logic_vector( 4 DOWNTO 0);
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+    SIGNAL s_reg_s:  std_logic_vector( 4 DOWNTO 0);
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+    SIGNAL s_reg_t:  std_logic_vector( 4 DOWNTO 0);
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+    SIGNAL s_reg_d:  std_logic_vector( 4 DOWNTO 0);
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     SIGNAL s_imm_a:  std_logic_vector( 4 DOWNTO 0);
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     SIGNAL s_imm_16: std_logic_vector(15 DOWNTO 0);
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     SIGNAL s_imm_26: std_logic_vector(25 DOWNTO 0);
... ... 
@@ -34,9 +34,9 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
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     COMPONENT e_mips_decoder IS
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         PORT (
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             i_instr:  IN  std_logic_vector(31 DOWNTO 0);
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-            o_src_s:  OUT std_logic_vector( 4 DOWNTO 0);
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-            o_src_t:  OUT std_logic_vector( 4 DOWNTO 0);
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-            o_dest:   OUT std_logic_vector( 4 DOWNTO 0);
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+            o_reg_s:  OUT std_logic_vector( 4 DOWNTO 0);
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+            o_reg_t:  OUT std_logic_vector( 4 DOWNTO 0);
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+            o_reg_d:  OUT std_logic_vector( 4 DOWNTO 0);
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             o_imm_a:  OUT std_logic_vector( 4 DOWNTO 0);
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             o_imm_16: OUT std_logic_vector(15 DOWNTO 0);
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             o_imm_26: OUT std_logic_vector(25 DOWNTO 0);
... ... 
@@ -76,9 +76,9 @@ BEGIN
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     decoder: e_mips_decoder
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         PORT MAP (
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             i_instr  => r_instr,
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-            o_src_s  => s_src_s,
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-            o_src_t  => s_src_t,
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-            o_dest   => s_dest,
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+            o_reg_s  => s_reg_s,
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+            o_reg_t  => s_reg_t,
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+            o_reg_d  => s_reg_d,
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             o_imm_a  => s_imm_a,
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             o_imm_16 => s_imm_16,
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             o_imm_26 => s_imm_26,
... ... 
@@ -93,11 +93,11 @@ BEGIN
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         PORT MAP (
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             rst         => rst,
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             clk         => clk,
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-            i_rd_a_no   => s_src_s,
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+            i_rd_a_no   => s_reg_s,
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             o_rd_a_data => s_op1,
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-            i_rd_b_no   => s_src_t,
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+            i_rd_b_no   => s_reg_t,
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             o_rd_b_data => s_op2,
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-            i_wr_no     => s_dest,
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+            i_wr_no     => s_reg_d,
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             i_wr_data   => s_res,
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             i_wr_en     => '1'
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         );
mips/decoder.vhd
View file @ cbae278
... ... 
@@ -6,9 +6,9 @@ USE work.mips_types.all;
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 ENTITY e_mips_decoder IS
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     PORT (
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         i_instr:  IN  std_logic_vector(31 DOWNTO 0);
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-        o_src_s:  OUT std_logic_vector( 4 DOWNTO 0);
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-        o_src_t:  OUT std_logic_vector( 4 DOWNTO 0);
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-        o_dest:   OUT std_logic_vector( 4 DOWNTO 0);
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+        o_reg_s:  OUT std_logic_vector( 4 DOWNTO 0);
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+        o_reg_t:  OUT std_logic_vector( 4 DOWNTO 0);
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+        o_reg_d:  OUT std_logic_vector( 4 DOWNTO 0);
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         o_imm_a:  OUT std_logic_vector( 4 DOWNTO 0);
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         o_imm_16: OUT std_logic_vector(15 DOWNTO 0);
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         o_imm_26: OUT std_logic_vector(25 DOWNTO 0);
... ... 
@@ -42,31 +42,31 @@ BEGIN
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         END CASE;
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     END PROCESS p_enc_type;
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-    p_src_s: PROCESS(i_instr, s_enc_type)
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+    p_reg_s: PROCESS(i_instr, s_enc_type)
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     BEGIN
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         CASE s_enc_type IS
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-            WHEN enc_reg => o_src_s <= i_instr(25 DOWNTO 21);
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-            WHEN enc_imm => o_src_s <= i_instr(25 DOWNTO 21);
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-            WHEN OTHERS  => o_src_s <= "00000";
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+            WHEN enc_reg => o_reg_s <= i_instr(25 DOWNTO 21);
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+            WHEN enc_imm => o_reg_s <= i_instr(25 DOWNTO 21);
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+            WHEN OTHERS  => o_reg_s <= "00000";
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         END CASE;
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-    END PROCESS p_src_s;
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+    END PROCESS p_reg_s;
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-    p_src_t: PROCESS(i_instr, s_enc_type)
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+    p_reg_t: PROCESS(i_instr, s_enc_type)
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     BEGIN
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         CASE s_enc_type IS
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-            WHEN enc_reg => o_src_t <= i_instr(20 DOWNTO 16);
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-            WHEN enc_imm => o_src_t <= i_instr(20 DOWNTO 16);
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-            WHEN OTHERS  => o_src_t <= "00000";
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+            WHEN enc_reg => o_reg_t <= i_instr(20 DOWNTO 16);
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+            WHEN enc_imm => o_reg_t <= i_instr(20 DOWNTO 16);
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+            WHEN OTHERS  => o_reg_t <= "00000";
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         END CASE;
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-    END PROCESS p_src_t;
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+    END PROCESS p_reg_t;
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-    p_dest: PROCESS(i_instr, s_enc_type)
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+    p_reg_d: PROCESS(i_instr, s_enc_type)
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     BEGIN
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         CASE s_enc_type IS
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-            WHEN enc_reg => o_dest <= i_instr(15 DOWNTO 11);
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-            WHEN OTHERS  => o_dest <= "00000";
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+            WHEN enc_reg => o_reg_d <= i_instr(15 DOWNTO 11);
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+            WHEN OTHERS  => o_reg_d <= "00000";
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         END CASE;
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-    END PROCESS p_dest;
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+    END PROCESS p_reg_d;
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     p_imm_a: PROCESS(i_instr, s_enc_type)
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     BEGIN
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