records for ethernet pins (b8449ce) - mips_sys · BlinkenArea

records for ethernet pins

Stefan Schuermans commited on 2012-04-08 12:45:21
Showing 5 changed files, with 82 additions and 81 deletions.

io/eth/eth.vhd 2374061..f3ca56d
io/eth/pins.vhd 0000000..c91ee22
mips_sys.xise ce0df45..250785e
system/system.vhd c4f90e2..4e4972d
test/testbed.vhd 22a27ca..1070046

io/eth/eth.vhd

@@ -6,6 +6,7 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
+USE work.io_eth_pins.all;
 
 ENTITY e_io_eth IS
     PORT (
@@ -23,15 +24,8 @@ ENTITY e_io_eth IS
         o_bm_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
         o_bm_wr_data: OUT std_logic_vector(31 DOWNTO 0);
         o_bm_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
-        pin_o_nrst:   OUT std_logic;
-        pin_i_rx_clk: IN  std_logic;
-        pin_i_rxd:    IN  std_logic_vector(4 DOWNTO 0);
-        pin_i_rx_dv:  IN  std_logic;
-        pin_i_crs:    IN  std_logic;
-        pin_i_col:    IN  std_logic;
-        pin_i_tx_clk: IN  std_logic;
-        pin_o_txd:    OUT std_logic_vector(3 DOWNTO 0);
-        pin_o_tx_en:  OUT std_logic
+        pin_o:        OUT t_io_eth_o_pins;
+        pin_i:        IN  t_io_eth_i_pins
     );
 END ENTITY e_io_eth;
 
@@ -219,7 +213,7 @@ BEGIN
         PORT MAP (
             rst        => rst,
             clk        => clk,
-            pin_o_nrst => pin_o_nrst
+            pin_o_nrst => pin_o.nrst
         );
 
     rxif: e_io_eth_rxif
@@ -230,11 +224,11 @@ BEGIN
             o_data_en    => s_rxif_data_en,
             o_done       => s_rxif_done,
             o_err        => s_rxif_err,
-            pin_i_rx_clk => pin_i_rx_clk,
-            pin_i_rxd    => pin_i_rxd,
-            pin_i_rx_dv  => pin_i_rx_dv,
-            pin_i_crs    => pin_i_crs,
-            pin_i_col    => pin_i_col
+            pin_i_rx_clk => pin_i.rx_clk,
+            pin_i_rxd    => pin_i.rxd,
+            pin_i_rx_dv  => pin_i.rx_dv,
+            pin_i_crs    => pin_i.crs,
+            pin_i_col    => pin_i.col
         );
 
     rxframe: e_io_eth_rxframe
@@ -355,9 +349,9 @@ BEGIN
             i_data       => s_txif_data,
             i_data_en    => s_txif_data_en,
             o_data_ack   => s_txif_data_ack,
-            pin_i_tx_clk => pin_i_tx_clk,
-            pin_o_txd    => pin_o_txd,
-            pin_o_tx_en  => pin_o_tx_en
+            pin_i_tx_clk => pin_i.tx_clk,
+            pin_o_txd    => pin_o.txd,
+            pin_o_tx_en  => pin_o.tx_en
         );
 
     txframe: e_io_eth_txframe

io/eth/pins.vhd

View file @ b8449ce

...	...	@@ -0,0 +1,30 @@
	1	+-- MIPS I system
	2	+-- Copyright 2011-2012 Stefan Schuermans <stefan@schuermans.info>
	3	+-- Copyleft GNU public license V2 or later
	4	+-- http://www.gnu.org/copyleft/gpl.html
	5	+
	6	+LIBRARY ieee;
	7	+USE ieee.std_logic_1164.all;
	8	+USE ieee.numeric_std.all;
	9	+
	10	+PACKAGE io_eth_pins IS
	11	+
	12	+ TYPE t_io_eth_o_pins IS
	13	+ RECORD
	14	+ nrst: std_logic;
	15	+ txd: std_logic_vector(3 DOWNTO 0);
	16	+ tx_en: std_logic;
	17	+ END RECORD;
	18	+
	19	+ TYPE t_io_eth_i_pins IS
	20	+ RECORD
	21	+ rx_clk: std_logic;
	22	+ rxd: std_logic_vector(4 DOWNTO 0);
	23	+ rx_dv: std_logic;
	24	+ crs: std_logic;
	25	+ col: std_logic;
	26	+ tx_clk: std_logic;
	27	+ END RECORD;
	28	+
	29	+END PACKAGE io_eth_pins;
	30	+

mips_sys.xise

View file @ b8449ce

@@ -29,7 +29,7 @@
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
@@ -53,7 +53,7 @@
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
@@ -63,11 +63,11 @@
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -77,11 +77,11 @@
     </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
@@ -92,19 +92,19 @@
     </file>
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
     </file>
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
     </file>
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
     </file>
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
     </file>
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
@@ -112,21 +112,21 @@
     </file>
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
@@ -134,7 +134,7 @@
     </file>
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
@@ -174,6 +174,10 @@
     <file xil_pn:name="memory_maps/mips_sys.bmm" xil_pn:type="FILE_BMM">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="io/eth/pins.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="226"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    </file>
   </files>
 
   <properties>

system/system.vhd

View file @ b8449ce

@@ -6,6 +6,7 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
+USE work.io_eth_pins.all;
 USE work.io_lcd_pins.all;
 USE work.io_switches_pins.all;
 
@@ -17,15 +18,8 @@ ENTITY e_system IS
         pin_i_switches: IN  t_io_switches_pins;
         pin_i_uart_rx:  IN  std_logic;
         pin_o_uart_tx:  OUT std_logic;
-        pin_o_eth_nrst:   OUT std_logic;
-        pin_i_eth_rx_clk: IN  std_logic;
-        pin_i_eth_rxd:    IN  std_logic_vector(4 DOWNTO 0);
-        pin_i_eth_rx_dv:  IN  std_logic;
-        pin_i_eth_crs:    IN  std_logic;
-        pin_i_eth_col:    IN  std_logic;
-        pin_i_eth_tx_clk: IN  std_logic;
-        pin_o_eth_txd:    OUT std_logic_vector(3 DOWNTO 0);
-        pin_o_eth_tx_en:  OUT std_logic
+        pin_o_eth:      OUT t_io_eth_o_pins;
+        pin_i_eth:      IN  t_io_eth_i_pins
     );
 END ENTITY e_system;
 
@@ -229,15 +223,8 @@ ARCHITECTURE a_system OF e_system IS
             o_bm_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
             o_bm_wr_data: OUT std_logic_vector(31 DOWNTO 0);
             o_bm_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
-            pin_o_nrst:   OUT std_logic;
-            pin_i_rx_clk: IN  std_logic;
-            pin_i_rxd:    IN  std_logic_vector(4 DOWNTO 0);
-            pin_i_rx_dv:  IN  std_logic;
-            pin_i_crs:    IN  std_logic;
-            pin_i_col:    IN  std_logic;
-            pin_i_tx_clk: IN  std_logic;
-            pin_o_txd:    OUT std_logic_vector(3 DOWNTO 0);
-            pin_o_tx_en:  OUT std_logic
+            pin_o:        OUT t_io_eth_o_pins;
+            pin_i:        IN  t_io_eth_i_pins
         );
     END COMPONENT e_io_eth;
 
@@ -516,15 +503,8 @@ BEGIN
             o_bm_rd_en   => s_ethbm_rd_en,
             o_bm_wr_data => s_ethbm_wr_data,
             o_bm_wr_en   => s_ethbm_wr_en,
-            pin_o_nrst   => pin_o_eth_nrst,
-            pin_i_rx_clk => pin_i_eth_rx_clk,
-            pin_i_rxd    => pin_i_eth_rxd,
-            pin_i_rx_dv  => pin_i_eth_rx_dv,
-            pin_i_crs    => pin_i_eth_crs,
-            pin_i_col    => pin_i_eth_col,
-            pin_i_tx_clk => pin_i_eth_tx_clk,
-            pin_o_txd    => pin_o_eth_txd,
-            pin_o_tx_en  => pin_o_eth_tx_en
+            pin_o        => pin_o_eth,
+            pin_i        => pin_i_eth
         );
 
     cyc_cnt: e_io_cyc_cnt

test/testbed.vhd

View file @ b8449ce

@@ -7,6 +7,7 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.numeric_std.all;
 USE std.textio.all;
+USE work.io_eth_pins.all;
 USE work.io_lcd_pins.all;
 USE work.io_switches_pins.all;
 
@@ -23,14 +24,8 @@ ARCHITECTURE a_testbed OF e_testbed IS
             pin_i_switches: IN  t_io_switches_pins;
             pin_i_uart_rx:  IN  std_logic;
             pin_o_uart_tx:  OUT std_logic;
-            pin_i_eth_rx_clk: IN  std_logic;
-            pin_i_eth_rxd:    IN  std_logic_vector(4 DOWNTO 0);
-            pin_i_eth_rx_dv:  IN  std_logic;
-            pin_i_eth_crs:    IN  std_logic;
-            pin_i_eth_col:    IN  std_logic;
-            pin_i_eth_tx_clk: IN  std_logic;
-            pin_o_eth_txd:    OUT std_logic_vector(3 DOWNTO 0);
-            pin_o_eth_tx_en:  OUT std_logic
+            pin_o_eth:      OUT t_io_eth_o_pins;
+            pin_i_eth:      IN  t_io_eth_i_pins
         );
     END COMPONENT e_system;
 
@@ -71,12 +66,11 @@ ARCHITECTURE a_testbed OF e_testbed IS
     SIGNAL s_leds:      std_logic_vector(7 DOWNTO 0);
     SIGNAL s_lcd:       t_io_lcd_pins;
     SIGNAL s_uart:      std_logic;
+    SIGNAL s_o_eth:     t_io_eth_o_pins;
+    SIGNAL s_i_eth:     t_io_eth_i_pins;
     SIGNAL s_eth_clk:   std_logic;
     SIGNAL s_eth_rxd_d: std_logic_vector(3 DOWNTO 0);
-    SIGNAL s_eth_rxd:   std_logic_vector(4 DOWNTO 0);
     SIGNAL s_eth_rx_dv: std_logic;
-    SIGNAL s_eth_txd:   std_logic_vector(3 DOWNTO 0);
-    SIGNAL s_eth_tx_en: std_logic;
 
 BEGIN
 
@@ -88,17 +82,16 @@ BEGIN
             pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0'),
             pin_i_uart_rx  => '1',
             pin_o_uart_tx  => s_uart,
-            pin_i_eth_rx_clk => s_eth_clk,
-            pin_i_eth_rxd    => s_eth_rxd,
-            pin_i_eth_rx_dv  => s_eth_rx_dv,
-            pin_i_eth_crs    => s_eth_rx_dv,
-            pin_i_eth_col    => '0',
-            pin_i_eth_tx_clk => s_eth_clk,
-            pin_o_eth_txd    => s_eth_txd,
-            pin_o_eth_tx_en  => s_eth_tx_en
+            pin_i_eth      => s_i_eth,
+            pin_o_eth      => s_o_eth
         );
 
-    s_eth_rxd <= "0" & s_eth_rxd_d;
+    s_i_eth.rx_clk <= s_eth_clk;
+    s_i_eth.rxd    <= "0" & s_eth_rxd_d;
+    s_i_eth.rx_dv  <= s_eth_rx_dv;
+    s_i_eth.crs    <= s_eth_rx_dv;
+    s_i_eth.col    <= '0';
+    s_i_eth.tx_clk <= s_eth_clk;
 
     p_clk: PROCESS
     BEGIN
@@ -144,9 +137,9 @@ BEGIN
         FOR i IN 0 TO eth_data'length - 1 LOOP
             WAIT UNTIL s_eth_clk = '0';
             WAIT UNTIL s_eth_clk = '1';
-            IF s_eth_tx_en = '1' THEN
+            IF s_o_eth.tx_en = '1' THEN
                 write(l, "ethernet TX: ");
-                write(l, to_integer(unsigned(s_eth_txd)));
+                write(l, to_integer(unsigned(s_o_eth.txd)));
                 writeline(output, l);
             END IF;
         END LOOP;


...	...	@@ -6,6 +6,7 @@
6	6	LIBRARY IEEE;
7	7	USE IEEE.STD_LOGIC_1164.ALL;
8	8	USE IEEE.NUMERIC_STD.ALL;
	9	+USE work.io_eth_pins.all;
9	10
10	11	ENTITY e_io_eth IS
11	12	PORT (
...	...	@@ -23,15 +24,8 @@ ENTITY e_io_eth IS
23	24	o_bm_rd_en: OUT std_logic_vector( 3 DOWNTO 0);
24	25	o_bm_wr_data: OUT std_logic_vector(31 DOWNTO 0);
25	26	o_bm_wr_en: OUT std_logic_vector( 3 DOWNTO 0);
26		- pin_o_nrst: OUT std_logic;
27		- pin_i_rx_clk: IN std_logic;
28		- pin_i_rxd: IN std_logic_vector(4 DOWNTO 0);
29		- pin_i_rx_dv: IN std_logic;
30		- pin_i_crs: IN std_logic;
31		- pin_i_col: IN std_logic;
32		- pin_i_tx_clk: IN std_logic;
33		- pin_o_txd: OUT std_logic_vector(3 DOWNTO 0);
34		- pin_o_tx_en: OUT std_logic
	27	+ pin_o: OUT t_io_eth_o_pins;
	28	+ pin_i: IN t_io_eth_i_pins
35	29	);
36	30	END ENTITY e_io_eth;
37	31
...	...	@@ -219,7 +213,7 @@ BEGIN
219	213	PORT MAP (
220	214	rst => rst,
221	215	clk => clk,
222		- pin_o_nrst => pin_o_nrst
	216	+ pin_o_nrst => pin_o.nrst
223	217	);
224	218
225	219	rxif: e_io_eth_rxif
...	...	@@ -230,11 +224,11 @@ BEGIN
230	224	o_data_en => s_rxif_data_en,
231	225	o_done => s_rxif_done,
232	226	o_err => s_rxif_err,
233		- pin_i_rx_clk => pin_i_rx_clk,
234		- pin_i_rxd => pin_i_rxd,
235		- pin_i_rx_dv => pin_i_rx_dv,
236		- pin_i_crs => pin_i_crs,
237		- pin_i_col => pin_i_col
	227	+ pin_i_rx_clk => pin_i.rx_clk,
	228	+ pin_i_rxd => pin_i.rxd,
	229	+ pin_i_rx_dv => pin_i.rx_dv,
	230	+ pin_i_crs => pin_i.crs,
	231	+ pin_i_col => pin_i.col
238	232	);
239	233
240	234	rxframe: e_io_eth_rxframe
...	...	@@ -355,9 +349,9 @@ BEGIN
355	349	i_data => s_txif_data,
356	350	i_data_en => s_txif_data_en,
357	351	o_data_ack => s_txif_data_ack,
358		- pin_i_tx_clk => pin_i_tx_clk,
359		- pin_o_txd => pin_o_txd,
360		- pin_o_tx_en => pin_o_tx_en
	352	+ pin_i_tx_clk => pin_i.tx_clk,
	353	+ pin_o_txd => pin_o.txd,
	354	+ pin_o_tx_en => pin_o.tx_en
361	355	);
362	356
363	357	txframe: e_io_eth_txframe

...	...	@@ -29,7 +29,7 @@
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31	31	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35	35	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
...	...	@@ -53,7 +53,7 @@
53	53	</file>
54	54	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55	55	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
56		- <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
	56	+ <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
57	57	</file>
58	58	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59	59	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
...	...	@@ -63,11 +63,11 @@
63	63	</file>
64	64	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65	65	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
66		- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
	66	+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
67	67	</file>
68	68	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69	69	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
71	71	</file>
72	72	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73	73	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -77,11 +77,11 @@
77	77	</file>
78	78	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79	79	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
80		- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
	80	+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
81	81	</file>
82	82	<file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83	83	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
84		- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
	84	+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
85	85	</file>
86	86	<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87	87	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
...	...	@@ -92,19 +92,19 @@
92	92	</file>
93	93	<file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94	94	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
95		- <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
	95	+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
96	96	</file>
97	97	<file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98	98	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
99		- <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
	99	+ <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
100	100	</file>
101	101	<file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102	102	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
103		- <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
	103	+ <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
104	104	</file>
105	105	<file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106	106	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
107		- <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
	107	+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
108	108	</file>
109	109	<file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110	110	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
...	...	@@ -112,21 +112,21 @@
112	112	</file>
113	113	<file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114	114	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
115		- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
	115	+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
116	116	</file>
117	117	<file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118	118	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119	119	</file>
120	120	<file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121	121	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
122		- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
	122	+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
123	123	</file>
124	124	<file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125	125	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126	126	</file>
127	127	<file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128	128	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
129		- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
	129	+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
130	130	</file>
131	131	<file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132	132	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
...	...	@@ -134,7 +134,7 @@
134	134	</file>
135	135	<file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136	136	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
137		- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
	137	+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
138	138	</file>
139	139	<file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140	140	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
...	...	@@ -174,6 +174,10 @@
174	174	<file xil_pn:name="memory_maps/mips_sys.bmm" xil_pn:type="FILE_BMM">
175	175	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
176	176	</file>
	177	+ <file xil_pn:name="io/eth/pins.vhd" xil_pn:type="FILE_VHDL">
	178	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="226"/>
	179	+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
	180	+ </file>
177	181	</files>
178	182
179	183	<properties>

...	...	@@ -7,6 +7,7 @@ LIBRARY ieee;
7	7	USE ieee.std_logic_1164.all;
8	8	USE ieee.numeric_std.all;
9	9	USE std.textio.all;
	10	+USE work.io_eth_pins.all;
10	11	USE work.io_lcd_pins.all;
11	12	USE work.io_switches_pins.all;
12	13
...	...	@@ -23,14 +24,8 @@ ARCHITECTURE a_testbed OF e_testbed IS
23	24	pin_i_switches: IN t_io_switches_pins;
24	25	pin_i_uart_rx: IN std_logic;
25	26	pin_o_uart_tx: OUT std_logic;
26		- pin_i_eth_rx_clk: IN std_logic;
27		- pin_i_eth_rxd: IN std_logic_vector(4 DOWNTO 0);
28		- pin_i_eth_rx_dv: IN std_logic;
29		- pin_i_eth_crs: IN std_logic;
30		- pin_i_eth_col: IN std_logic;
31		- pin_i_eth_tx_clk: IN std_logic;
32		- pin_o_eth_txd: OUT std_logic_vector(3 DOWNTO 0);
33		- pin_o_eth_tx_en: OUT std_logic
	27	+ pin_o_eth: OUT t_io_eth_o_pins;
	28	+ pin_i_eth: IN t_io_eth_i_pins
34	29	);
35	30	END COMPONENT e_system;
36	31
...	...	@@ -71,12 +66,11 @@ ARCHITECTURE a_testbed OF e_testbed IS
71	66	SIGNAL s_leds: std_logic_vector(7 DOWNTO 0);
72	67	SIGNAL s_lcd: t_io_lcd_pins;
73	68	SIGNAL s_uart: std_logic;
	69	+ SIGNAL s_o_eth: t_io_eth_o_pins;
	70	+ SIGNAL s_i_eth: t_io_eth_i_pins;
74	71	SIGNAL s_eth_clk: std_logic;
75	72	SIGNAL s_eth_rxd_d: std_logic_vector(3 DOWNTO 0);
76		- SIGNAL s_eth_rxd: std_logic_vector(4 DOWNTO 0);
77	73	SIGNAL s_eth_rx_dv: std_logic;
78		- SIGNAL s_eth_txd: std_logic_vector(3 DOWNTO 0);
79		- SIGNAL s_eth_tx_en: std_logic;
80	74
81	75	BEGIN
82	76
...	...	@@ -88,17 +82,16 @@ BEGIN
88	82	pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0'),
89	83	pin_i_uart_rx => '1',
90	84	pin_o_uart_tx => s_uart,
91		- pin_i_eth_rx_clk => s_eth_clk,
92		- pin_i_eth_rxd => s_eth_rxd,
93		- pin_i_eth_rx_dv => s_eth_rx_dv,
94		- pin_i_eth_crs => s_eth_rx_dv,
95		- pin_i_eth_col => '0',
96		- pin_i_eth_tx_clk => s_eth_clk,
97		- pin_o_eth_txd => s_eth_txd,
98		- pin_o_eth_tx_en => s_eth_tx_en
	85	+ pin_i_eth => s_i_eth,
	86	+ pin_o_eth => s_o_eth
99	87	);
100	88
101		- s_eth_rxd <= "0" & s_eth_rxd_d;
	89	+ s_i_eth.rx_clk <= s_eth_clk;
	90	+ s_i_eth.rxd <= "0" & s_eth_rxd_d;
	91	+ s_i_eth.rx_dv <= s_eth_rx_dv;
	92	+ s_i_eth.crs <= s_eth_rx_dv;
	93	+ s_i_eth.col <= '0';
	94	+ s_i_eth.tx_clk <= s_eth_clk;
102	95
103	96	p_clk: PROCESS
104	97	BEGIN
...	...	@@ -144,9 +137,9 @@ BEGIN
144	137	FOR i IN 0 TO eth_data'length - 1 LOOP
145	138	WAIT UNTIL s_eth_clk = '0';
146	139	WAIT UNTIL s_eth_clk = '1';
147		- IF s_eth_tx_en = '1' THEN
	140	+ IF s_o_eth.tx_en = '1' THEN
148	141	write(l, "ethernet TX: ");
149		- write(l, to_integer(unsigned(s_eth_txd)));
	142	+ write(l, to_integer(unsigned(s_o_eth.txd)));
150	143	writeline(output, l);
151	144	END IF;
152	145	END LOOP;
153	146