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420617e
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master
mips_sys
fw
rom.head.vhd
added "LEDs" I/O peripheral changed instruction memory from dpram to generated rom improved firmware structure to generate rom VHDL code
Stefan Schuermans
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420617e
at 2012-02-10 22:43:28
rom.head.vhd
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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY e_rom IS GENERIC ( addr_width: INTEGER ); PORT ( clk: IN std_logic; i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0); o_data: OUT std_logic_vector( 31 DOWNTO 0) ); END ENTITY e_rom; ARCHITECTURE a_rom OF e_rom IS SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0); SUBTYPE t_data IS std_logic_vector( 31 DOWNTO 0); TYPE t_buf IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data; SIGNAL s_buf: t_buf := (
