LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY e_rom IS
    GENERIC (
        addr_width: INTEGER
    );
    PORT (
        clk:    IN  std_logic;
        i_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
        o_data: OUT std_logic_vector(            31 DOWNTO 0)
    );
END ENTITY e_rom;

ARCHITECTURE a_rom OF e_rom IS

    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
    SUBTYPE t_data IS std_logic_vector(            31 DOWNTO 0);
    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;

    SIGNAL s_buf: t_buf := (