mips_sys

mips/mul.vhd        1) LIBRARY ieee;
mips/mul.vhd        2) USE ieee.std_logic_1164.all;
mips/mul.vhd        3) USE ieee.numeric_std.all;
mips/mul.vhd        4) USE work.mips_types.all;
mips/mul.vhd        5) 
mips/mul.vhd        6) ENTITY e_mips_mul IS
mips/mul.vhd        7)     PORT (
mips/mul.vhd        8)         rst:      IN  std_logic;
mips/mul.vhd        9)         clk:      IN  std_logic;
mips/mul.vhd       10)         i_a:      IN  std_logic_vector(31 DOWNTO 0);
mips/mul.vhd       11)         i_b:      IN  std_logic_vector(31 DOWNTO 0);
mips/mul.vhd       12)         i_signed: IN  std_logic;
mips/mul.vhd       13)         i_start:  IN  std_logic;
mips/mul.vhd       14)         o_busy:   OUT std_logic;
mips/mul.vhd       15)         o_res:    OUT std_logic_vector(63 DOWNTO 0)
mips/mul.vhd       16)     );
mips/mul.vhd       17) END ENTITY e_mips_mul;
mips/mul.vhd       18) 
mips/mul.vhd       19) ARCHITECTURE a_mips_mul OF e_mips_mul IS
mips/mul.vhd       20) 
mips/mul.vhd       21)     TYPE t_state IS (idle, state_1, state_2, state_3, state_4, post);
mips/mul.vhd       22)     SIGNAL n_state: t_state;

mips/mul_fast.vhd  23)     SIGNAL r_state: t_state := idle;

mips/mul.vhd       24) 
mips/mul.vhd       25)     SIGNAL n_a:   unsigned(31 DOWNTO 0);
mips/mul.vhd       26)     SIGNAL n_b:   unsigned(31 DOWNTO 0);
mips/mul.vhd       27)     SIGNAL n_neg: boolean;
mips/mul.vhd       28)     SIGNAL n_res: unsigned(63 DOWNTO 0);

mips/mul_fast.vhd  29)     SIGNAL r_a:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
mips/mul_fast.vhd  30)     SIGNAL r_b:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
mips/mul_fast.vhd  31)     SIGNAL r_neg: boolean               := false;
mips/mul_fast.vhd  32)     SIGNAL r_res: unsigned(63 DOWNTO 0) := (OTHERS => '0');