MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
read peripherals with one cycle delay - as for memory
fe7741d @ 2012-02-12 19:10:11
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|---|---|---|
| cyc_cnt.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd_pins.vhd | implemented LCD peripheral | 2012-02-12 15:31:45 |
| leds.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |