MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
improve 200ms tick and task processing, get rid of UART output of received ethernet frames
e5fcec6 @ 2012-03-24 19:05:42
| .. | ||
|---|---|---|
| crc32.vhd | implemented ethernet RX CRC check | 2012-03-03 17:09:36 |
| fifo.vhd | improve synchonous FIFO implementation (get rid of delays between reads) | 2012-03-11 18:59:11 |
| fifo_dc.vhd | remove leftover comments | 2012-03-11 18:44:23 |
| rwram.vhd | added FIFO to UART TX | 2012-02-20 13:00:00 |
| rwram_dc.vhd | added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing | 2012-03-10 10:50:55 |