MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
clock and reset constraints are for whole system
a086ce1 @ 2012-02-10 23:22:30
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| testbed.vhd | added "LEDs" I/O peripheral changed instruction memory from dpram to generated rom improved firmware structure to generate rom VHDL code | 2012-02-10 22:43:28 |