MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
converted core to use req and grant signals to access data bus
77114e6 @ 2012-03-01 21:23:47
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| system.vhd | changed MIPS core to use read and write ack instead of stall input | 2012-02-29 21:28:37 |