Stefan Schuermans
read peripherals with one cycle delay - as for memory
Stefan Schuermans commited fe7741d at 2012-02-12 19:10:11
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.io_lcd_pins.all;
ENTITY e_io_lcd IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
i_wr_data: IN std_logic_vector(31 DOWNTO 0);
i_wr_en: IN std_logic_vector( 3 DOWNTO 0);
pin_o_lcd: OUT t_io_lcd_pins
);
END ENTITY e_io_lcd;
ARCHITECTURE a_io_lcd OF e_io_lcd IS
SIGNAL n_lcd: t_io_lcd_pins;
SIGNAL r_lcd: t_io_lcd_pins := (data => (OTHERS => '0'),
e => '0', rs => '0', rw => '0');
BEGIN
p_next: PROCESS(r_lcd, i_wr_data, i_wr_en)
BEGIN
IF i_wr_en(0) = '1' THEN
n_lcd.data <= i_wr_data(7 DOWNTO 0);
ELSE
n_lcd.data <= r_lcd.data;
END IF;
IF i_wr_en(1) = '1' THEN
n_lcd.e <= i_wr_data(8);
ELSE
n_lcd.e <= r_lcd.e;
END IF;
IF i_wr_en(2) = '1' THEN
n_lcd.rs <= i_wr_data(16);
ELSE
n_lcd.rs <= r_lcd.rs;
END IF;
IF i_wr_en(3) = '1' THEN
n_lcd.rw <= i_wr_data(24);
ELSE
n_lcd.rw <= r_lcd.rw;
END IF;
END PROCESS p_next;
p_sync: PROCESS(rst, clk)
BEGIN
IF rst = '1' THEN
 
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