mips_sys

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY e_block_fifo IS
    GENERIC (
        addr_width: natural;
        data_width: natural
    );
    PORT (
        rst:       IN  std_logic;
        clk:       IN  std_logic;
        o_wr_rdy:  OUT std_logic;
        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
        i_wr_en:   IN  std_logic;
        o_rd_rdy:  OUT std_logic;
        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
        i_rd_en:   IN  std_logic
    );
END ENTITY e_block_fifo;
ARCHITECTURE a_block_fifo OF e_block_fifo IS
    COMPONENT e_block_rwram
        GENERIC (
            addr_width: natural;
            data_width: natural := 8
        );
        PORT (
            clk:       IN  std_logic;
            i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
            i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
            i_wr_en:   IN  std_logic
        );
    END COMPONENT e_block_rwram;
    SUBTYPE t_pos  IS natural RANGE 0 TO 2 ** addr_width - 1;
    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
    SIGNAL r_begin:         t_pos     := 0;
    SIGNAL n_begin:         t_pos;
    SIGNAL s_begin_addr:    t_addr;
    SIGNAL s_begin_sn_addr: t_addr; -- _sn_ means sometimes next
    SIGNAL s_rd_rdy:        std_logic;
    SIGNAL s_rd_en:         std_logic;
    SIGNAL r_end:            t_pos     := 0;
    SIGNAL n_end:            t_pos;
 
 
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