LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY e_io_eth_rxif IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
o_data: OUT std_logic_vector(7 DOWNTO 0);
o_data_en: OUT std_logic;
o_done: OUT std_logic;
o_err: OUT std_logic;
pin_i_rx_clk: IN std_logic;
pin_i_rxd: IN std_logic_vector(4 DOWNTO 0);
pin_i_rx_dv: IN std_logic;
pin_i_crs: IN std_logic;
pin_i_col: IN std_logic
);
END ENTITY e_io_eth_rxif;
ARCHITECTURE a_io_eth_rxif OF e_io_eth_rxif IS
TYPE t_in_state IS (in_idle, in_nibble, in_data, in_pre_done, in_done,
in_pre_err, in_err, in_post_err);
SIGNAL r_in_state: t_in_state := in_idle;
SIGNAL r_in_data: std_logic_vector(7 DOWNTO 0) := X"00";
SIGNAL s_fifo_wr_rdy: std_logic;
SIGNAL s_fifo_wr_data: std_logic_vector(9 DOWNTO 0);
SIGNAL s_fifo_wr_en: std_logic;
SIGNAL s_fifo_rd_rdy: std_logic;
SIGNAL s_fifo_rd_data: std_logic_vector(9 DOWNTO 0);
COMPONENT e_block_fifo_dc IS
GENERIC (
addr_width: natural;
data_width: natural
);
PORT (
rst: IN std_logic;
wr_clk: IN std_logic;
o_wr_rdy: OUT std_logic;
i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
i_wr_en: IN std_logic;
rd_clk: IN std_logic;
o_rd_rdy: OUT std_logic;
o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
i_rd_en: IN std_logic
);
END COMPONENT e_block_fifo_dc;
