io/eth/rxif.vhd (7ea541c) - mips_sys · BlinkenArea

7ea541c877463e1d810ebd434aa3e777e53f661a

begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	1) LIBRARY IEEE; 2) USE IEEE.STD_LOGIC_1164.ALL; 3) USE IEEE.NUMERIC_STD.ALL; 4) 5) ENTITY e_io_eth_rxif IS 6) PORT ( 7) rst: IN std_logic; 8) clk: IN std_logic; 9) o_data: OUT std_logic_vector(7 DOWNTO 0); 10) o_data_en: OUT std_logic; 11) o_done: OUT std_logic; 12) o_err: OUT std_logic; 13) pin_i_rx_clk: IN std_logic; 14) pin_i_rxd: IN std_logic_vector(4 DOWNTO 0); 15) pin_i_rx_dv: IN std_logic; 16) pin_i_crs: IN std_logic; 17) pin_i_col: IN std_logic 18) ); 19) END ENTITY e_io_eth_rxif; 20) 21) ARCHITECTURE a_io_eth_rxif OF e_io_eth_rxif IS 22) 23) TYPE t_in_state IS (in_idle, in_nibble, in_data, in_pre_done, in_done, 24) in_pre_err, in_err, in_post_err); 25) 26) SIGNAL r_in_state: t_in_state := in_idle; 27) SIGNAL r_in_data: std_logic_vector(7 DOWNTO 0) := X"00"; 28)
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	29) SIGNAL s_fifo_wr_rdy: std_logic; 30) SIGNAL s_fifo_wr_data: std_logic_vector(9 DOWNTO 0); 31) SIGNAL s_fifo_wr_en: std_logic; 32) SIGNAL s_fifo_rd_rdy: std_logic; 33) SIGNAL s_fifo_rd_data: std_logic_vector(9 DOWNTO 0); 34) 35) COMPONENT e_block_fifo_dc IS 36) GENERIC ( 37) addr_width: natural; 38) data_width: natural 39) ); 40) PORT ( 41) rst: IN std_logic; 42) wr_clk: IN std_logic; 43) o_wr_rdy: OUT std_logic; 44) i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0); 45) i_wr_en: IN std_logic; 46) rd_clk: IN std_logic; 47) o_rd_rdy: OUT std_logic; 48) o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0); 49) i_rd_en: IN std_logic 50) ); 51) END COMPONENT e_block_fifo_dc;
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	52) 53) BEGIN 54) 55) p_in: PROCESS(rst, pin_i_rx_clk) 56) BEGIN 57) IF rst = '1' THEN 58) r_in_state <= in_idle; 59) r_in_data <= X"00"; 60) ELSIF rising_edge(pin_i_rx_clk) THEN 61) CASE r_in_state IS 62) WHEN in_idle => 63) IF pin_i_col = '1' THEN 64) r_in_state <= in_pre_err; 65) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN 66) IF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err 67) r_in_state <= in_pre_err; 68) ELSE 69) r_in_state <= in_nibble; 70) r_in_data(3 DOWNTO 0) <= pin_i_rxd(3 DOWNTO 0); 71) END IF; 72) END IF; 73) WHEN in_nibble => 74) IF pin_i_col = '1' THEN 75) r_in_state <= in_err; 76) ELSIF pin_i_crs = '0' OR pin_i_rx_dv = '0' THEN 77) r_in_state <= in_err; 78) ELSIF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err 79) r_in_state <= in_err; 80) ELSE 81) r_in_state <= in_data; 82) r_in_data(7 DOWNTO 4) <= pin_i_rxd(3 DOWNTO 0); 83) END IF; 84) WHEN in_data => 85) IF pin_i_col = '1' THEN 86) r_in_state <= in_pre_err; 87) ELSIF pin_i_crs = '0' OR pin_i_rx_dv = '0' THEN 88) r_in_state <= in_pre_done; 89) ELSIF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err 90) r_in_state <= in_pre_err; 91) ELSE 92) r_in_state <= in_nibble; 93) r_in_data(3 DOWNTO 0) <= pin_i_rxd(3 DOWNTO 0); 94) END IF; 95) WHEN in_pre_done => 96) IF pin_i_col = '1' THEN 97) r_in_state <= in_err; 98) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN 99) r_in_state <= in_err; 100) ELSE 101) r_in_state <= in_done; 102) END IF; 103) WHEN in_done => 104) IF pin_i_col = '1' THEN 105) r_in_state <= in_pre_err; 106) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN 107) r_in_state <= in_err; 108) ELSE 109) r_in_state <= in_idle; 110) END IF; 111) WHEN in_pre_err => 112) r_in_state <= in_err; 113) WHEN in_err => 114) r_in_state <= in_post_err; 115) WHEN in_post_err =>
more consistent DV and CRS... Stefan Schuermans authored 12 years ago	`116) IF pin_i_col = '0' AND 117) (pin_i_crs = '0' OR pin_i_rx_dv = '0') THEN`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`118) r_in_state <= in_idle; 119) END IF; 120) WHEN OTHERS => NULL; 121) END CASE; 122) END IF; 123) END PROCESS p_in; 124)`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`125) p_wr_fifo: PROCESS(r_in_state, r_in_data, s_fifo_wr_rdy)`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`126) BEGIN`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`127) s_fifo_wr_data <= (OTHERS => '0'); 128) s_fifo_wr_en <= '0'; 129) IF s_fifo_wr_rdy = '1' THEN`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`130) CASE r_in_state IS 131) WHEN in_data =>`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`132) s_fifo_wr_data(7 DOWNTO 0) <= r_in_data; 133) s_fifo_wr_en <= '1';`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`134) WHEN in_done =>`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`135) s_fifo_wr_data(8) <= '1'; 136) s_fifo_wr_en <= '1';`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`137) WHEN in_err =>`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`138) s_fifo_wr_data(9) <= '1'; 139) s_fifo_wr_en <= '1';`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`140) WHEN OTHERS => NULL; 141) END CASE; 142) END IF;`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	143) END PROCESS p_wr_fifo; 144) 145) fifo: e_block_fifo_dc 146) GENERIC MAP ( 147) addr_width => 2, 148) data_width => 10 149) ) 150) PORT MAP ( 151) rst => rst, 152) wr_clk => pin_i_rx_clk, 153) o_wr_rdy => s_fifo_wr_rdy, 154) i_wr_data => s_fifo_wr_data, 155) i_wr_en => s_fifo_wr_en, 156) rd_clk => clk, 157) o_rd_rdy => s_fifo_rd_rdy, 158) o_rd_data => s_fifo_rd_data, 159) i_rd_en => s_fifo_rd_rdy 160) ); 161) 162) o_data <= s_fifo_rd_data(7 DOWNTO 0); 163) o_data_en <= s_fifo_rd_rdy; 164) o_done <= s_fifo_rd_data(8); 165) o_err <= s_fifo_rd_data(9);