io/eth/rxif.vhd (902aa40) - mips_sys · BlinkenArea

902aa402b3830b9c9aa26758390b6eb93b42a0f5

added file headers Stefan Schuermans authored 12 years ago	`1) -- MIPS I system`
replace email address in he... Stefan Schuermans authored 12 years ago	`2) -- Copyright 2011-2012 Stefan Schuermans <stefan@blinkenarea.org>`
added file headers Stefan Schuermans authored 12 years ago	`3) -- Copyleft GNU public license V2 or later 4) -- http://www.gnu.org/copyleft/gpl.html 5)`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	6) LIBRARY IEEE; 7) USE IEEE.STD_LOGIC_1164.ALL; 8) USE IEEE.NUMERIC_STD.ALL; 9) 10) ENTITY e_io_eth_rxif IS 11) PORT ( 12) rst: IN std_logic; 13) clk: IN std_logic; 14) o_data: OUT std_logic_vector(7 DOWNTO 0); 15) o_data_en: OUT std_logic; 16) o_done: OUT std_logic; 17) o_err: OUT std_logic; 18) pin_i_rx_clk: IN std_logic; 19) pin_i_rxd: IN std_logic_vector(4 DOWNTO 0); 20) pin_i_rx_dv: IN std_logic; 21) pin_i_crs: IN std_logic; 22) pin_i_col: IN std_logic 23) ); 24) END ENTITY e_io_eth_rxif; 25) 26) ARCHITECTURE a_io_eth_rxif OF e_io_eth_rxif IS 27) 28) TYPE t_in_state IS (in_idle, in_nibble, in_data, in_pre_done, in_done, 29) in_pre_err, in_err, in_post_err); 30) 31) SIGNAL r_in_state: t_in_state := in_idle; 32) SIGNAL r_in_data: std_logic_vector(7 DOWNTO 0) := X"00"; 33)
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	34) SIGNAL s_fifo_wr_rdy: std_logic; 35) SIGNAL s_fifo_wr_data: std_logic_vector(9 DOWNTO 0); 36) SIGNAL s_fifo_wr_en: std_logic; 37) SIGNAL s_fifo_rd_rdy: std_logic; 38) SIGNAL s_fifo_rd_data: std_logic_vector(9 DOWNTO 0); 39) 40) COMPONENT e_block_fifo_dc IS 41) GENERIC ( 42) addr_width: natural; 43) data_width: natural 44) ); 45) PORT ( 46) rst: IN std_logic; 47) wr_clk: IN std_logic; 48) o_wr_rdy: OUT std_logic; 49) i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0); 50) i_wr_en: IN std_logic; 51) rd_clk: IN std_logic; 52) o_rd_rdy: OUT std_logic; 53) o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0); 54) i_rd_en: IN std_logic 55) ); 56) END COMPONENT e_block_fifo_dc;
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	57) 58) BEGIN 59) 60) p_in: PROCESS(rst, pin_i_rx_clk) 61) BEGIN 62) IF rst = '1' THEN 63) r_in_state <= in_idle; 64) r_in_data <= X"00"; 65) ELSIF rising_edge(pin_i_rx_clk) THEN 66) CASE r_in_state IS 67) WHEN in_idle => 68) IF pin_i_col = '1' THEN 69) r_in_state <= in_pre_err; 70) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN 71) IF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err 72) r_in_state <= in_pre_err; 73) ELSE 74) r_in_state <= in_nibble; 75) r_in_data(3 DOWNTO 0) <= pin_i_rxd(3 DOWNTO 0); 76) END IF; 77) END IF; 78) WHEN in_nibble => 79) IF pin_i_col = '1' THEN 80) r_in_state <= in_err; 81) ELSIF pin_i_crs = '0' OR pin_i_rx_dv = '0' THEN 82) r_in_state <= in_err; 83) ELSIF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err 84) r_in_state <= in_err; 85) ELSE 86) r_in_state <= in_data; 87) r_in_data(7 DOWNTO 4) <= pin_i_rxd(3 DOWNTO 0); 88) END IF; 89) WHEN in_data => 90) IF pin_i_col = '1' THEN 91) r_in_state <= in_pre_err; 92) ELSIF pin_i_crs = '0' OR pin_i_rx_dv = '0' THEN 93) r_in_state <= in_pre_done; 94) ELSIF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err 95) r_in_state <= in_pre_err; 96) ELSE 97) r_in_state <= in_nibble; 98) r_in_data(3 DOWNTO 0) <= pin_i_rxd(3 DOWNTO 0); 99) END IF; 100) WHEN in_pre_done => 101) IF pin_i_col = '1' THEN 102) r_in_state <= in_err; 103) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN 104) r_in_state <= in_err; 105) ELSE 106) r_in_state <= in_done; 107) END IF; 108) WHEN in_done => 109) IF pin_i_col = '1' THEN 110) r_in_state <= in_pre_err; 111) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN 112) r_in_state <= in_err; 113) ELSE 114) r_in_state <= in_idle; 115) END IF; 116) WHEN in_pre_err => 117) r_in_state <= in_err; 118) WHEN in_err => 119) r_in_state <= in_post_err; 120) WHEN in_post_err =>
more consistent DV and CRS... Stefan Schuermans authored 12 years ago	`121) IF pin_i_col = '0' AND 122) (pin_i_crs = '0' OR pin_i_rx_dv = '0') THEN`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`123) r_in_state <= in_idle; 124) END IF; 125) WHEN OTHERS => NULL; 126) END CASE; 127) END IF; 128) END PROCESS p_in; 129)`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`130) p_wr_fifo: PROCESS(r_in_state, r_in_data, s_fifo_wr_rdy)`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`131) BEGIN`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`132) s_fifo_wr_data <= (OTHERS => '0'); 133) s_fifo_wr_en <= '0'; 134) IF s_fifo_wr_rdy = '1' THEN`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`135) CASE r_in_state IS 136) WHEN in_data =>`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`137) s_fifo_wr_data(7 DOWNTO 0) <= r_in_data; 138) s_fifo_wr_en <= '1';`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`139) WHEN in_done =>`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`140) s_fifo_wr_data(8) <= '1'; 141) s_fifo_wr_en <= '1';`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`142) WHEN in_err =>`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	`143) s_fifo_wr_data(9) <= '1'; 144) s_fifo_wr_en <= '1';`
begin of ethernet RX implem... Stefan Schuermans authored 12 years ago	`145) WHEN OTHERS => NULL; 146) END CASE; 147) END IF;`
replaced ethernet RX clock... Stefan Schuermans authored 12 years ago	148) END PROCESS p_wr_fifo; 149) 150) fifo: e_block_fifo_dc 151) GENERIC MAP ( 152) addr_width => 2, 153) data_width => 10 154) ) 155) PORT MAP ( 156) rst => rst, 157) wr_clk => pin_i_rx_clk, 158) o_wr_rdy => s_fifo_wr_rdy, 159) i_wr_data => s_fifo_wr_data, 160) i_wr_en => s_fifo_wr_en, 161) rd_clk => clk, 162) o_rd_rdy => s_fifo_rd_rdy, 163) o_rd_data => s_fifo_rd_data, 164) i_rd_en => s_fifo_rd_rdy 165) ); 166) 167) o_data <= s_fifo_rd_data(7 DOWNTO 0); 168) o_data_en <= s_fifo_rd_rdy; 169) o_done <= s_fifo_rd_data(8); 170) o_err <= s_fifo_rd_data(9);