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b8449ce
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master
mips_sys
mips_sys.xise
records for ethernet pins
Stefan Schuermans
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b8449ce
at 2012-04-08 12:45:21
mips_sys.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> <header> <!-- ISE source project file created by Project Navigator. --> <!-- --> <!-- This file contains project source information including a list of --> <!-- project source files, project and process properties. This file, --> <!-- along with the project source files, is sufficient to open and --> <!-- implement in ISE Project Navigator. --> <!-- --> <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> </header> <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> <files> <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/> </file> <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/> </file> <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="22"/> </file> <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/> </file> <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> <association xil_pn:name="Implementation" xil_pn:seqID="34"/> </file> <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/> </file> <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/> </file> <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/> </file> <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file 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xil_pn:name="Implementation" xil_pn:seqID="33"/> </file> <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> <association xil_pn:name="Implementation" xil_pn:seqID="32"/> </file> <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/> </file> <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> <association xil_pn:name="Implementation" xil_pn:seqID="30"/> </file> <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/> </file> <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/> </file> <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> <association xil_pn:name="Implementation" xil_pn:seqID="23"/> </file> <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/> </file> <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/> </file> <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> <association xil_pn:name="Implementation" xil_pn:seqID="19"/> </file> <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> <association xil_pn:name="Implementation" xil_pn:seqID="17"/> </file> <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> <association 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<file xil_pn:name="io/eth/pins.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="226"/> <association xil_pn:name="Implementation" xil_pn:seqID="20"/> </file> </files> <properties> <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Auto 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xil_pn:value="mips_sys.ipf" xil_pn:valueState="non-default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|e_testbed|a_testbed" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-23T20:57:37" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="504447C81FC3113F3078F816935626AA" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> </properties> <bindings> <binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/lcd.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/switches.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/uart.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/eth.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="memory_maps/mips_sys.bmm"/> </bindings> <libraries/> <autoManagedFiles> <!-- The following files are identified by `include statements in verilog --> <!-- source files and are automatically managed by Project Navigator. --> <!-- --> <!-- Do not hand-edit this section, as it will be overwritten when the --> <!-- project is analyzed based on files automatically identified as --> <!-- include files. --> </autoManagedFiles> </project>
