olympus_trigger

initial checkin of Olympus trigger tools
Stefan Schuermans

Stefan Schuermans commited on 2013-10-26 20:14:19
Showing 12 changed files, with 3950 additions and 0 deletions.

ir_trigger/README
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+IR trigger for Olympus camera
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+Copyright (C) 2013 Stefan Schuermans <stefan@blinkenarea.org>
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+Copyleft: GNU public license - http://www.gnu.org/copyleft/gpl.html
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+a BlinkenArea project - http://www.blinkenarea.org/
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+
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+This project is an IR trigger for an Olympus camera. It is able to generate
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+the infrared (IR) signal to make an Olympus camera focus and take a picture.
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+The code is written for an ATtiny2313 microcontroller running with an 8MHz
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+external crystal. It will output the signal on port pin RB0. The IR LED has
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+to be connected between this pin and ground.
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+
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+The code in the current configuration will output a "take picture" command
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+every second. However, this can be changed easily by modifying the main loop.
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+there is also code to send the "key held" command, but it is currently
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+commented out. You should treat this code as a building block for your
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+project or as a proof-of-concept. It is not intended to be market-ready.
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+
ir_trigger/firmware/.gitignore
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+*.cof
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+*.hex
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+*.lst
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+*.obj
ir_trigger/firmware/Makefile
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+NAME = ir_trigger
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+INC = tn2313def
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+
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+LFUSE = 0x9F
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+HFUSE = 0xDF
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+EFUSE = 0xFF
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+LOCK = 0xFC
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+
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+#PROGRAMMER = stk200
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+#CONNECTION = /dev/parport0
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+PROGRAMMER = avrisp2
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+CONNECTION = usb
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+DEVICE = t2313
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+
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+AVRA = avra
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+AVRDUDE = avrdude
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+
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+AVRDUDE_CALL = $(AVRDUDE) -c $(PROGRAMMER) -P $(CONNECTION) -p $(DEVICE)
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+
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+.PHONY: all prog prog_fuses prog_auto clean
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+.SUFFIXES:
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+
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+all: $(NAME).hex
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+
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+$(NAME).hex: $(NAME).asm $(INC).inc Makefile
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+	$(AVRA) -l $(NAME).lst $(NAME).asm
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+
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+prog_fuses: Makefile
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+	$(AVRDUDE_CALL) -u -e
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+	$(AVRDUDE_CALL) -u -U lfuse:w:$(LFUSE):m -U hfuse:w:$(HFUSE):m \
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+	                   -U efuse:w:$(EFUSE):m
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+
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+prog: $(NAME).hex Makefile
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+	$(AVRDUDE_CALL) -u -e
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+	$(AVRDUDE_CALL) -u -U flash:w:$(NAME).hex
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+	$(AVRDUDE_CALL) -u -V -U lock:w:$(LOCK):m
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+
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+prog_auto: $(NAME).hex Makefile
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+	while ! $(MAKE) prog_fuses || ! $(MAKE) prog; do echo -n; done
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+
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+clean:
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+	rm -f $(addprefix $(NAME)., lst obj cof hex eep.hex)
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+
ir_trigger/firmware/ir_trigger.asm
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+; IR trigger for Olympus camera
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+; Copyright (C) 2013 Stefan Schuermans <stefan@blinkenarea.org>
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+; Copyleft: GNU public license - http://www.gnu.org/copyleft/gpl.html
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+; a BlinkenArea project - http://www.blinkenarea.org/
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+
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+; code for 8 MHz crystal osciallator
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+
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+.INCLUDE        "tn2313def.inc"
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+
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+
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+.def    TMP                     =       r16
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+.def    CNT                     =       r17
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+.def    CNT2                    =       r18
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+.def    DATA                    =       r19
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+
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+
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+.equ    IR_PORT                 =       PORTB
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+.equ    IR_BIT                  =       0
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+
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+
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+
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+.DSEG
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+.ORG    0x060
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+
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+
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+
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+.CSEG
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+.ORG    0x000
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+        rjmp    ENTRY                   ; RESET
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+        reti                            ; INT0
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+        reti                            ; INT1
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+        reti                            ; TIMER1_CAPT
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+        reti                            ; TIMER1_COMPA
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+        reti                            ; TIMER1_OVF
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+        reti                            ; TIMER0_OVF
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+        reti                            ; USART0_RX
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+        reti                            ; USART0_UDRE
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+        reti                            ; USART0_TX
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+        reti                            ; ANALOG_COMP
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+        reti                            ; PC_INT0
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+        reti                            ; TIMER1_COMPB
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+        reti                            ; TIMER0_COMPA
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+        reti                            ; TIMER0_COMPB
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+        reti                            ; USI_START
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+        reti                            ; USI_OVERFLOW
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+        reti                            ; EE_READY
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+        reti                            ; WDT
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+        reti                            ; PC_INT1
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+        reti                            ; PC_INT2
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+
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+
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+
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+; code entry point
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+ENTRY:
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+; set system clock prescaler to 1:1, i.e. run at 8 MHz
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+        ldi     TMP,1<<CLKPCE
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+        out     CLKPR,TMP
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+        ldi     TMP,0
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+        out     CLKPR,TMP
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+; initialize output ports
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+        ldi     TMP,0x00                ; PA[01] to output, low
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+        out     PORTA,TMP
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+        ldi     TMP,0x03
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+        out     DDRA,TMP
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+        ldi     TMP,0xA0                ; PB[0-46] to output, low - PB[57] to input, pull-up enabled
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+        out     PORTB,TMP
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+        ldi     TMP,0x5F
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+        out     DDRB,TMP
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+        ldi     TMP,0x00                ; PD[0-6] to output, low
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+        out     PORTD,TMP
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+        ldi     TMP,0x7F
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+        out     DDRD,TMP
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+; initialize stack pointer
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+        ldi     TMP,RAMEND
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+        out     SPL,TMP
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+; enable watchdog (64ms)
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+        wdr
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+        ldi     TMP,1<<WDCE|1<<WDE
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+        out     WDTCR,TMP
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+        ldi     TMP,1<<WDE|1<<WDP1
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+        out     WDTCR,TMP
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+        wdr
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+; disable analog comparator
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+        ldi     TMP,1<<ACD
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+        out     ACSR,TMP
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+; jump to main program
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+        rjmp    MAIN
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+
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+
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+
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+; output CNT pulses with 38kHz, 1/4 duty-cycle
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+IR_PULSE:
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+        sbi     IR_PORT,IR_BIT          ; IR = 1, 2 cyc
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+        ldi     TMP,13                  ; 51 cyc
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+IR_PULSE_WAIT_1:
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+        wdr
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+        dec     TMP
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+        brne    IR_PULSE_WAIT_1
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+        cbi     IR_PORT,IR_BIT          ; IR = 0, 2 cyc
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+        ldi     TMP,38                  ; 155 cyc
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+IR_PULSE_WAIT_0:
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+        wdr
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+        dec     TMP
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+        brne    IR_PULSE_WAIT_0
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+        dec     CNT                     ; next pulse
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+        brne    IR_PULSE
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+        ret                             ; done
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+
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+
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+
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+; wait 10us
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+WAIT_10US:
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+        ldi     TMP,18
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+WAIT_10US_LOOP:
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+        wdr
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+        dec     TMP
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+        brne    WAIT_10US_LOOP
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+        nop
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+        ret
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+
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+
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+
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+; output a bit (DATA,0) over IR
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+IR_OUT_BIT:
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+        ldi     CNT,21                  ; ouput 560us pulses
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+        rcall   IR_PULSE
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+        ldi     CNT,56                  ; bit 0 -> wait 560us
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+        sbrc    DATA,0
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+        ldi     CNT,169                 ; bit 1 -> wait 1690us
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+IR_OUT_BIT_WAIT:
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+        rcall   WAIT_10US
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+        dec     CNT
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+        brne    IR_OUT_BIT_WAIT
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+        ret                             ; done
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+
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+
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+
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+; output a byte (DATA)
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+IR_BYTE:
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+        push    DATA                    ; save data
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+        ldi     CNT2,8                  ; iterate 8 bit
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+IR_BYTE_LOOP:
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+        rcall   IR_OUT_BIT              ; output bit
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+        lsr     DATA                    ; next bit
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+        dec     CNT2
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+        brne    IR_BYTE_LOOP
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+        pop     DATA                    ; restore data
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+        ret                             ; done
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+
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+
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+
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+; output IR start burst
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+IR_START:
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+        ldi     CNT,171                 ; ouput 9ms pulses
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+        rcall   IR_PULSE
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+        ldi     CNT,171
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+        rcall   IR_PULSE
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+        ldi     CNT,225                 ; wait 4.5ms
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+IR_START_LOOP:
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+        rcall   WAIT_10US
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+        rcall   WAIT_10US
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+        dec     CNT
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+        brne    IR_START_LOOP
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+        ret                             ; done
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+
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+
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+
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+; output IR key hold burst
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+IR_HOLD:
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+        ldi     CNT,171                 ; ouput 9ms pulses
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+        rcall   IR_PULSE
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+        ldi     CNT,171
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+        rcall   IR_PULSE
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+        ldi     CNT,225                 ; wait 2.25ms
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+IR_HOLD_LOOP:
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+        rcall   WAIT_10US
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+        dec     CNT
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+        brne    IR_HOLD_LOOP
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+        ldi     CNT,1                   ; ouput 1 pulse
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+        rcall   IR_PULSE
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+        ret                             ; done
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+
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+
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+
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+; main program
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+MAIN:
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+        wdr
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+
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+; main loop
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+MAIN_LOOP:
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+        wdr
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+
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+; shutter E-330 and E-620 reverse engineered
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+        rcall   IR_START
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+        ldi     DATA,0x86
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+        rcall   IR_BYTE
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+        ldi     DATA,0x3B
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+        rcall   IR_BYTE
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+        ldi     DATA,0x01
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+        rcall   IR_BYTE
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+        ldi     DATA,0xFE
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+        rcall   IR_BYTE
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+        clr     DATA
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+        rcall   IR_OUT_BIT
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+
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+; key hold impulse
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+;        rcall   IR_START
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+;        clr     DATA
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+;        rcall   IR_OUT_BIT
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+
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+; wait 1s
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+        clr     CNT2
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+        clr     CNT
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+MAIN_WAIT:
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+        rcall   WAIT_10US
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+        rcall   WAIT_10US
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+        dec     CNT
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+        brne    MAIN_WAIT
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+        dec     CNT2
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+        brne    MAIN_WAIT
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+
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+; bottom of main loop
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+        rjmp     MAIN_LOOP
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+
ir_trigger/firmware/tn2313def.inc
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+;***************************************************************************
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+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
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+;*
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+;* Number           :AVR000
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+;* File Name        :"tn2313def.inc"
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+;* Title            :Register/Bit Definitions for the ATtiny2313
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+;* Date             :03.06.17
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+;* Version          :1.00
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+;* Support E-mail   :avr@atmel.com
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+;* Target MCU       :ATtiny2313
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+;*
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+;* DESCRIPTION
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+;* When including this file in the assembly program file, all I/O register
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+;* names and I/O register bit names appearing in the data book can be used.
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+;* In addition, the two registers forming the data pointer Z have been
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+;* assigned names ZL - ZH.
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+;*
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+;* The Register names are represented by their hexadecimal address.
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+;*
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+;* The Register Bit names are represented by their bit number (0-7).
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+;*
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+;* Please observe the difference in using the bit names with instructions
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+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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+;* (skip if bit in register set/cleared). The following example illustrates
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+;* this:
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+;*
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+;* in   r16,PORTB       ;read PORTB latch
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+;* sbr  r16,(1<<PB6)+(1<<PB5)   ;set PB6 and PB5 (use masks, not bit#)
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+;* out  PORTB,r16       ;output to PORTB
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+;*
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+;* in   r16,TIFR        ;read the Timer Interrupt Flag Register
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+;* sbrc r16,TOV0        ;test the overflow flag (use bit#)
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+;* rjmp TOV0_is_set     ;jump if set
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+;* ...                  ;otherwise do something else
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+;*
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+;***************************************************************************
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+
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+;***** Specify Device
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+.device ATtiny2313
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+
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+
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+;*****************************************************************************
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+; I/O Register Definitions
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+;*****************************************************************************
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+
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+.equ    SREG    = 0x3F
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+.equ    SPL     = 0x3D
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+.equ    OCR0B   = 0x3C
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+.equ    GIMSK   = 0x3B
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+.equ    EIFR    = 0x3A
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+.equ    GIFR    = 0x3A      ; for compatibility purpose
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+.equ    TIMSK   = 0x39
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+.equ    TIFR    = 0x38
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+.equ    SPMCSR  = 0x37
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+.equ    OCR0A   = 0x36
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+.equ    MCUCR   = 0x35
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+.equ    MCUSR   = 0x34
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+.equ    TCCR0B  = 0x33
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+.equ    TCCR0   = 0x33      ; for compatibility purpose
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+.equ    TCNT0   = 0x32
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+.equ    OSCCAL  = 0x31
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+.equ    TCCR0A  = 0x30
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+.equ    TCCR1A  = 0x2F
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+.equ    TCCR1B  = 0x2E
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+.equ    TCNT1H  = 0x2D
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+.equ    TCNT1L  = 0x2C
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+.equ    OCR1AH  = 0x2B
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+.equ    OCR1AL  = 0x2A
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+.equ    OCR1BH  = 0x29
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+.equ    OCR1BL  = 0x28
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+.equ    CLKPR   = 0x26
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+.equ    ICR1H   = 0x25
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+.equ    ICR1L   = 0x24
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+.equ    SFIOR   = 0x23
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+.equ    TCCR1C  = 0x22
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+.equ    WDTCR   = 0x21
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+.equ    PCMSK   = 0x20
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+.equ    EEAR    = 0x1E      ; for compatibility purpose
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+.equ    EEARL   = 0x1E
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+.equ    EEDR    = 0x1D
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+.equ    EECR    = 0x1C
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+.equ    PORTA   = 0x1B
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+.equ    DDRA    = 0x1A
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+.equ    PINA    = 0x19
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+.equ    PORTB   = 0x18
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+.equ    DDRB    = 0x17
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+.equ    PINB    = 0x16
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+.equ    GPIOR2  = 0x15
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+.equ    GPIOR1  = 0x14
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+.equ    GPIOR0  = 0x13
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+.equ    PORTD   = 0x12
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+.equ    DDRD    = 0x11
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+.equ    PIND    = 0x10
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+.equ    USIDR   = 0x0F
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+.equ    USISR   = 0x0E
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+.equ    USICR   = 0x0D
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+.equ    UDR     = 0x0C
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+.equ    UCSRA   = 0x0B
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+.equ    USR     = 0x0B      ; for compatibility purpose
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+.equ    UCSRB   = 0x0A
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+.equ    UCR     = 0x0A      ; for compatibility purpose
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+.equ    UBRRL   = 0x09
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+.equ    UBRR    = 0x09      ; for compatibility purpose
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+.equ    ACSR    = 0x08
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+.equ    UCSRC   = 0x03
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+.equ    UBRRH   = 0x02
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+.equ    DIDR    = 0x01
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+
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+
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+;*****************************************************************************
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+; Bit Definitions
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+;*****************************************************************************
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+
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+;***** SREG *******
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+.equ I          = 7
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+.equ T          = 6
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+.equ H          = 5
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+.equ S          = 4
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+.equ V          = 3
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+.equ N          = 2
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+;.equ Z          = 1
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+.equ C          = 0
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+
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+;***** SPL ********
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+.equ SP7        = 7
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+.equ SP6        = 6
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+.equ SP5        = 5
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+.equ SP4        = 4
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+.equ SP3        = 3
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+.equ SP2        = 2
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+.equ SP1        = 1
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+.equ SP0        = 0
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+
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+;***** GIMSK ******
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+.equ INT1       = 7
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+.equ INT0       = 6
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+.equ PCIE       = 5
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+
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+;***** EIFR *******
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+.equ INTF1      = 7
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+.equ INTF0      = 6
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+.equ PCIF       = 5
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+
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+;***** TIMSK ******
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+.equ TOIE1      = 7
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+.equ OCIE1A     = 6
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+.equ OCIE1B     = 5
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+.equ ICIE1      = 3
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+.equ OCIE0B     = 2
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+.equ TOIE0      = 1
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+.equ OCIE0A     = 0
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+.equ TICIE      = 3     ; for compatibility purpose
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+
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+;***** TIFR *******
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+.equ TOV1       = 7
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+.equ OCF1A      = 6
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+.equ OCF1B      = 5
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+.equ ICF1       = 3
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+.equ OCF0B      = 2
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+.equ TOV0       = 1
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+.equ OCF0A      = 0
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+
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+;***** SPMCSR *****
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+.equ CTPB       = 4
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+.equ RFLB       = 3
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+.equ PGWRT      = 2
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+.equ PGERS      = 1
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+.equ SPMEN      = 0
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+
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+;***** MCUCR ******
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+.equ PUD        = 7
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+.equ SM1        = 6
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+.equ SE         = 5
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+.equ SM0        = 4
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+.equ ISC11      = 3
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+.equ ISC10      = 2
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+.equ ISC01      = 1
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+.equ ISC00      = 0
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+.equ SM         = 4     ; for compatibility purpose
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+
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+;***** MCUSR ******
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+.equ WDRF       = 3
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+.equ BORF       = 2
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+.equ EXTRF      = 1
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+.equ PORF       = 0
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+
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+;***** TCCR0B *****
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+.equ FOC0A      = 7
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+.equ FOC0B      = 6
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+.equ WGM02      = 3
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+.equ CS02       = 2
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+.equ CS01       = 1
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+.equ CS00       = 0
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+
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+;***** OSCCAL *****
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+.equ CAL6       = 6
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+.equ CAL5       = 5
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+.equ CAL4       = 4
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+.equ CAL3       = 3
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+.equ CAL2       = 2
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+.equ CAL1       = 1
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+.equ CAL0       = 0
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+
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+;***** TCCR0A *****
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+.equ COM0A1     = 7
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+.equ COM0A0     = 6
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+.equ COM0B1     = 5
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+.equ COM0B0     = 4
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+.equ WGM01      = 1
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+.equ WGM00      = 0
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+
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+;***** TCCR1A *****
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+.equ COM1A1     = 7
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+.equ COM1A0     = 6
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+.equ COM1B1     = 5
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+.equ COM1B0     = 4
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+.equ WGM11      = 1
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+.equ WGM10      = 0
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+.equ PWM11      = 1     ; for compatibility purpose
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+.equ PWM10      = 0     ; for compatibility purpose
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+
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+;***** TCCR1B *****
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+.equ ICNC1      = 7
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+.equ ICES1      = 6
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+.equ WGM13      = 4
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+.equ WGM12      = 3
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+.equ CS12       = 2
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+.equ CS11       = 1
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+.equ CS10       = 0
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+.equ CTC1       = 3     ; for compatibility purpose
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+
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+;***** CLKPR ******
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+.equ CLKPCE     = 7
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+.equ CLKPS3     = 3
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+.equ CLKPS2     = 2
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+.equ CLKPS1     = 1
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+.equ CLKPS0     = 0
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+
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+;***** SFIOR ******
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+.equ PSR10      = 0
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+
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+;***** TCCR1C *****
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+.equ FOC1A      = 7
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+.equ FOC1B      = 6
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+
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+;***** WDTCSR *****
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+.equ WDIF       = 7
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+.equ WDIE       = 6
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+.equ WDP3       = 5
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+.equ WDCE       = 4
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+.equ WDE        = 3
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+.equ WDP2       = 2
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+.equ WDP1       = 1
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+.equ WDP0       = 0
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+.equ WDTOE      = 4
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+
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+;***** PCMSK ******
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+.equ PCINT7     = 7
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+.equ PCINT6     = 6
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+.equ PCINT5     = 5
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+.equ PCINT4     = 4
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+.equ PCINT3     = 3
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+.equ PCINT2     = 2
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+.equ PCINT1     = 1
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+.equ PCINT0     = 0
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+
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+;***** EECR *******
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+.equ EEPM1      = 5
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+.equ EEPM0      = 4
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+.equ EERIE      = 3
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+.equ EEMPE      = 2
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+.equ EEPE       = 1
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+.equ EERE       = 0
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+; Kept for backward compatibility
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+.equ EEMWE      = 2
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+.equ EEWE       = 1
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+
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+
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+;***** PORTA ******
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+.equ PORTA2     = 2
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+.equ PORTA1     = 1
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+.equ PORTA0     = 0
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+
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+;***** DDRA *******
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+.equ DDA2       = 2
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+.equ DDA1       = 1
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+.equ DDA0       = 0
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+
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+;***** PINA *******
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+.equ PINA2      = 2
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+.equ PINA1      = 1
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+.equ PINA0      = 0
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+
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+;***** PORTB ******
295 
+.equ PORTB7     = 7
296 
+.equ PORTB6     = 6
297 
+.equ PORTB5     = 5
298 
+.equ PORTB4     = 4
299 
+.equ PORTB3     = 3
300 
+.equ PORTB2     = 2
301 
+.equ PORTB1     = 1
302 
+.equ PORTB0     = 0
303 
+
304 
+;***** DDRB *******
305 
+.equ DDB7       = 7
306 
+.equ DDB6       = 6
307 
+.equ DDB5       = 5
308 
+.equ DDB4       = 4
309 
+.equ DDB3       = 3
310 
+.equ DDB2       = 2
311 
+.equ DDB1       = 1
312 
+.equ DDB0       = 0
313 
+
314 
+;***** PINB *******
315 
+.equ PINB7      = 7
316 
+.equ PINB6      = 6
317 
+.equ PINB5      = 5
318 
+.equ PINB4      = 4
319 
+.equ PINB3      = 3
320 
+.equ PINB2      = 2
321 
+.equ PINB1      = 1
322 
+.equ PINB0      = 0
323 
+
324 
+;***** PORTD ******
325 
+.equ PORTD6     = 6
326 
+.equ PORTD5     = 5
327 
+.equ PORTD4     = 4
328 
+.equ PORTD3     = 3
329 
+.equ PORTD2     = 2
330 
+.equ PORTD1     = 1
331 
+.equ PORTD0     = 0
332 
+
333 
+;***** DDRD *******
334 
+.equ DDD6       = 6
335 
+.equ DDD5       = 5
336 
+.equ DDD4       = 4
337 
+.equ DDD3       = 3
338 
+.equ DDD2       = 2
339 
+.equ DDD1       = 1
340 
+.equ DDD0       = 0
341 
+
342 
+;***** PIND *******
343 
+.equ PIND6      = 6
344 
+.equ PIND5      = 5
345 
+.equ PIND4      = 4
346 
+.equ PIND3      = 3
347 
+.equ PIND2      = 2
348 
+.equ PIND1      = 1
349 
+.equ PIND0      = 0
350 
+
351 
+;***** USISR ******
352 
+.equ USISIF     = 7
353 
+.equ USIOIF     = 6
354 
+.equ USIPF      = 5
355 
+.equ USIDC      = 4
356 
+.equ USICNT3    = 3
357 
+.equ USICNT2    = 2
358 
+.equ USICNT1    = 1
359 
+.equ USICNT0    = 0
360 
+
361 
+;***** USICR ******
362 
+.equ USISIE     = 7
363 
+.equ USIOIE     = 6
364 
+.equ USIWM1     = 5
365 
+.equ USIWM0     = 4
366 
+.equ USICS1     = 3
367 
+.equ USICS0     = 2
368 
+.equ USICLK     = 1
369 
+.equ USITC      = 0
370 
+
371 
+;***** UCSRA ******
372 
+.equ RXC        = 7
373 
+.equ TXC        = 6
374 
+.equ UDRE       = 5
375 
+.equ FE         = 4
376 
+.equ DOR        = 3
377 
+.equ UPE	= 2
378 
+.equ PE         = 2	; for compatibility purpose
379 
+.equ U2X        = 1
380 
+.equ MPCM       = 0
381 
+;.equ OR         = 3     ; for compatibility purpose
382 
+
383 
+;***** UCSRB ******
384 
+.equ RXCIE      = 7
385 
+.equ TXCIE      = 6
386 
+.equ UDRIE      = 5
387 
+.equ RXEN       = 4
388 
+.equ TXEN       = 3
389 
+.equ UCSZ2      = 2
390 
+.equ RXB8       = 1
391 
+.equ TXB8       = 0
392 
+.equ CHR9       = 2     ; for compatibility purpose
393 
+
394 
+;***** ACSR *******
395 
+.equ ACD        = 7
396 
+.equ ACBG       = 6
397 
+.equ ACO        = 5
398 
+.equ ACI        = 4
399 
+.equ ACIE       = 3
400 
+.equ ACIC       = 2
401 
+.equ ACIS1      = 1
402 
+.equ ACIS0      = 0
403 
+
404 
+;***** UCSRC ******
405 
+.equ UMSEL      = 6
406 
+.equ UPM1       = 5
407 
+.equ UPM0       = 4
408 
+.equ USBS       = 3
409 
+.equ UCSZ1      = 2
410 
+.equ UCSZ0      = 1
411 
+.equ UCPOL      = 0
412 
+
413 
+;***** DIDR ******
414 
+.equ AIN1D      = 1
415 
+.equ AIN0D      = 0
416 
+
417 
+;*****************************************************************************
418 
+; CPU Register Declarations
419 
+;*****************************************************************************
420 
+
421 
+.def    XL      = r26       ; X pointer low
422 
+.def    XH      = r27       ; X pointer high
423 
+.def    YL      = r28       ; Y pointer low
424 
+.def    YH      = r29       ; Y pointer high
425 
+.def    ZL      = r30       ; Z pointer low
426 
+.def    ZH      = r31       ; Z pointer high
427 
+
428 
+
429 
+;*****************************************************************************
430 
+; Data Memory Declarations
431 
+;*****************************************************************************
432 
+
433 
+.equ    RAMEND      = 0xDF  ; Highest internal data memory (SRAM) address.
434 
+                            ;(128 Bytes RAM + IO + REG)
435 
+.equ    EEPROMEND   = 0x7F  ; Highest EEPROM address.
436 
+                            ;(128 Bytes)
437 
+.equ    EEADRBITS   =   7   ; no. of bits in EEPROM address register
438 
+
439 
+.equ    RAM_SIZE    = 128
440 
+
441 
+
442 
+;*****************************************************************************
443 
+; Program Memory Declarations
444 
+;*****************************************************************************
445 
+
446 
+.equ    FLASHEND    = 0x3FF ;  Highest program memory (flash) address
447 
+                            ; (When addressed as 16 bit words)
448 
+                            ; ( 1024 words , 2K byte )
449 
+
450 
+;**** Page Size ****
451 
+.equ    PAGESIZE    = 16    ;number of WORDS in a Flash page
452 
+.equ    EEPAGESIZE  =  2    ;number of WORDS in an EEPROM page
453 
+
454 
+;*****************************************************************************
455 
+;**** Interrupt Vectors ****
456 
+;*****************************************************************************
457 
+
458 
+.equ    INT0addr        = 0x001     ;External Interrupt0
459 
+.equ    INT1addr        = 0x002     ;External Interrupt1
460 
+.equ    ICP1addr        = 0x003     ;Input capture interrupt 1
461 
+.equ    OC1Aaddr        = 0x004     ;Timer/Counter1 Compare Match A
462 
+.equ    OVF1addr        = 0x005     ;Overflow1 Interrupt
463 
+.equ    OVF0addr        = 0x006     ;Overflow0 Interrupt
464 
+.equ    URXC0addr       = 0x007     ;USART0 RX Complete Interrupt
465 
+.equ    UDRE0addr       = 0x008     ;USART0 Data Register Empty Interrupt
466 
+.equ    UTXC0addr       = 0x009     ;USART0 TX Complete Interrupt
467 
+.equ    ACIaddr         = 0x00A     ;Analog Comparator Interrupt
468 
+.equ    PCINTaddr       = 0x00B     ;Pin Change Interrupt
469 
+.equ    OC1Baddr        = 0x00C     ;Timer/Counter1 Compare Match B
470 
+.equ    OC0Aaddr        = 0x00D     ;Timer/Counter0 Compare Match A
471 
+.equ    OC0Baddr        = 0x00E     ;Timer/Counter0 Compare Match B
472 
+.equ    USI_STARTaddr   = 0x00F     ;USI start interrupt
473 
+.equ    USI_OVFaddr     = 0x010     ;USI overflow interrupt
474 
+.equ    ERDYaddr        = 0x011     ;EEPROM write complete
475 
+.equ    WDTaddr         = 0x012     ;Watchdog Timer Interrupt
476 
+		; for compatibility purpose
477 
+.equ	URXCaddr		= 0x007
478 
+.equ	UDREaddr		= 0x008
479 
+.equ	UTXCaddr		= 0x009
480 
+
481 
+;*****************************************************************************
482 
+;*****************************************************************************
time_trigger/README
View file @ a149600
... ... 
@@ -0,0 +1,23 @@
1 
+time trigger for Olympus camera
2 
+Copyright (C) 2013 Stefan Schuermans <stefan@blinkenarea.org>
3 
+Copyleft: GNU public license - http://www.gnu.org/copyleft/gpl.html
4 
+a BlinkenArea project - http://www.blinkenarea.org/
5 
+
6 
+This project is an external trigger circuit for an Olympus camera. It is able
7 
+to detect an object passing a light barrier and will trigger the camera after
8 
+a configurable amount of time via a cable, mimicking an wire-bound external
9 
+trigger button.
10 
+
11 
+Two potentiometers are used to configure the delay between the detection of
12 
+the object by the light barrier and the output of the trigger impulse to
13 
+the camera. One potentiometer is for coarse grained time setting and the
14 
+other one for fine-tuning.
15 
+To configure the time, set the fine-grain potentiometer to middle position,
16 
+then try to set the time using the coarse-grain potentiometer as precise as
17 
+you can. Afterwards, modify the fine-grain potentiometer to get the time
18 
+exactly right.
19 
+The delay can be configured from a few milliseconds to about one second.
20 
+
21 
+The schematic in the electrics directory is drawn using gEDA gschem:
22 
+http://wiki.geda-project.org/geda:gaf
23 
+
time_trigger/electrics/.gitignore
View file @ a149600
... ... 
@@ -0,0 +1,3 @@
1 
+*~
2 
+*.pdf
3 
+*.ps
time_trigger/electrics/time_trigger.sch
View file @ a149600
... ... 
@@ -0,0 +1,2377 @@
1 
+v 20110115 2
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+pintype=io
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+}
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+pinlabel=PB4 (MISO)
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+T 38450 42200 5 8 0 1 0 8 1
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+pintype=io
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+}
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+P 38800 42000 38500 42000 1 0 0
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+{
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+T 38450 42000 9 8 1 1 0 6 1
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+T 38450 42000 5 8 0 1 0 8 1
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+pintype=io
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+}
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+P 38800 41800 38500 41800 1 0 0
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+{
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+pinlabel=PB2 (nSS/OC1B)
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+T 38450 41800 5 8 0 1 0 8 1
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+pintype=io
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+}
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+P 38800 41600 38500 41600 1 0 0
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+{
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+T 38600 41650 5 8 1 1 0 0 1
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+T 38450 41600 9 8 1 1 0 6 1
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+pinlabel=PB1 (OC1A)
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+T 38450 41600 5 8 0 1 0 8 1
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+}
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+{
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+T 38450 41400 9 8 1 1 0 6 1
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+pinlabel=PB0 (ICP1)
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+T 38450 41400 5 8 0 1 0 8 1
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+pintype=io
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+}
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+P 38800 41000 38500 41000 1 0 0
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+{
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+T 38600 41050 5 8 1 1 0 0 1
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+T 38600 40950 5 8 0 1 0 2 1
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+T 38450 41000 9 8 1 1 0 6 1
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+pinlabel=PC5 (ADC5/SCL)
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+T 38450 41000 5 8 0 1 0 8 1
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+pintype=io
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+}
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+P 38800 40800 38500 40800 1 0 0
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+{
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+T 38600 40850 5 8 1 1 0 0 1
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93 
+T 38600 40750 5 8 0 1 0 2 1
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+pinseq=27
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+T 38450 40800 9 8 1 1 0 6 1
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+pinlabel=PC4 (ADC4/SDA)
97 
+T 38450 40800 5 8 0 1 0 8 1
98 
+pintype=io
99 
+}
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+P 38800 40600 38500 40600 1 0 0
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+{
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+T 38600 40650 5 8 1 1 0 0 1
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104 
+T 38600 40550 5 8 0 1 0 2 1
105 
+pinseq=26
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+T 38450 40600 9 8 1 1 0 6 1
107 
+pinlabel=PC3 (ADC3)
108 
+T 38450 40600 5 8 0 1 0 8 1
109 
+pintype=io
110 
+}
111 
+P 38800 40400 38500 40400 1 0 0
112 
+{
113 
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114 
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+T 38600 40350 5 8 0 1 0 2 1
116 
+pinseq=25
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+T 38450 40400 9 8 1 1 0 6 1
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+pinlabel=PC2 (ADC2)
119 
+T 38450 40400 5 8 0 1 0 8 1
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+pintype=io
121 
+}
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+{
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125 
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126 
+T 38600 40150 5 8 0 1 0 2 1
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+pinseq=24
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+T 38450 40200 9 8 1 1 0 6 1
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+pinlabel=PC1 (ADC1)
130 
+T 38450 40200 5 8 0 1 0 8 1
131 
+pintype=io
132 
+}
133 
+P 38800 40000 38500 40000 1 0 0
134 
+{
135 
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136 
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137 
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+T 38450 40000 9 8 1 1 0 6 1
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+pinlabel=PC0 (ADC0)
141 
+T 38450 40000 5 8 0 1 0 8 1
142 
+pintype=io
143 
+}
144 
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+{
146 
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147 
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149 
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150 
+T 38450 39600 9 8 1 1 0 6 1
151 
+pinlabel=PD7 (AIN1)
152 
+T 38450 39600 5 8 0 1 0 8 1
153 
+pintype=io
154 
+}
155 
+P 38800 39400 38500 39400 1 0 0
156 
+{
157 
+T 38600 39450 5 8 1 1 0 0 1
158 
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159 
+T 38600 39350 5 8 0 1 0 2 1
160 
+pinseq=12
161 
+T 38450 39400 9 8 1 1 0 6 1
162 
+pinlabel=PD6 (AIN0)
163 
+T 38450 39400 5 8 0 1 0 8 1
164 
+pintype=io
165 
+}
166 
+P 38800 39200 38500 39200 1 0 0
167 
+{
168 
+T 38600 39250 5 8 1 1 0 0 1
169 
+pinnumber=11
170 
+T 38600 39150 5 8 0 1 0 2 1
171 
+pinseq=11
172 
+T 38450 39200 9 8 1 1 0 6 1
173 
+pinlabel=PD5 (T1)
174 
+T 38450 39200 5 8 0 1 0 8 1
175 
+pintype=io
176 
+}
177 
+P 38800 39000 38500 39000 1 0 0
178 
+{
179 
+T 38600 39050 5 8 1 1 0 0 1
180 
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181 
+T 38600 38950 5 8 0 1 0 2 1
182 
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183 
+T 38450 39000 9 8 1 1 0 6 1
184 
+pinlabel=PD4 (XCK/T0)
185 
+T 38450 39000 5 8 0 1 0 8 1
186 
+pintype=io
187 
+}
188 
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189 
+{
190 
+T 38600 38850 5 8 1 1 0 0 1
191 
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192 
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193 
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194 
+T 38450 38800 9 8 1 1 0 6 1
195 
+pinlabel=PD3 (INT1)
196 
+T 38450 38800 5 8 0 1 0 8 1
197 
+pintype=io
198 
+}
199 
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200 
+{
201 
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202 
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203 
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204 
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205 
+T 38450 38600 9 8 1 1 0 6 1
206 
+pinlabel=PD2 (INT0)
207 
+T 38450 38600 5 8 0 1 0 8 1
208 
+pintype=io
209 
+}
210 
+P 38800 38400 38500 38400 1 0 0
211 
+{
212 
+T 38600 38450 5 8 1 1 0 0 1
213 
+pinnumber=3
214 
+T 38600 38350 5 8 0 1 0 2 1
215 
+pinseq=3
216 
+T 38450 38400 9 8 1 1 0 6 1
217 
+pinlabel=PD1 (TXD)
218 
+T 38450 38400 5 8 0 1 0 8 1
219 
+pintype=io
220 
+}
221 
+P 38800 38200 38500 38200 1 0 0
222 
+{
223 
+T 38600 38250 5 8 1 1 0 0 1
224 
+pinnumber=2
225 
+T 38600 38150 5 8 0 1 0 2 1
226 
+pinseq=2
227 
+T 38450 38200 9 8 1 1 0 6 1
228 
+pinlabel=PD0 (RXD)
229 
+T 38450 38200 5 8 0 1 0 8 1
230 
+pintype=io
231 
+}
232 
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233 
+{
234 
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235 
+pinnumber=22
236 
+T 35200 38150 5 8 0 1 0 8 1
237 
+pinseq=22
238 
+T 35350 38200 9 8 1 1 0 0 1
239 
+pinlabel=GND2
240 
+T 35350 38200 5 8 0 1 0 2 1
241 
+pintype=pwr
242 
+}
243 
+P 35000 38400 35300 38400 1 0 0
244 
+{
245 
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246 
+pinnumber=8
247 
+T 35200 38350 5 8 0 1 0 8 1
248 
+pinseq=8
249 
+T 35350 38400 9 8 1 1 0 0 1
250 
+pinlabel=GND1
251 
+T 35350 38400 5 8 0 1 0 2 1
252 
+pintype=pwr
253 
+}
254 
+P 35000 42000 35300 42000 1 0 0
255 
+{
256 
+T 35200 42050 5 8 1 1 0 6 1
257 
+pinnumber=7
258 
+T 35200 41950 5 8 0 1 0 8 1
259 
+pinseq=7
260 
+T 35350 42000 9 8 1 1 0 0 1
261 
+pinlabel=VCC
262 
+T 35350 42000 5 8 0 1 0 2 1
263 
+pintype=pwr
264 
+}
265 
+P 35000 42400 35300 42400 1 0 0
266 
+{
267 
+T 35200 42450 5 8 1 1 0 6 1
268 
+pinnumber=20
269 
+T 35200 42350 5 8 0 1 0 8 1
270 
+pinseq=20
271 
+T 35350 42400 9 8 1 1 0 0 1
272 
+pinlabel=AVCC
273 
+T 35350 42400 5 8 0 1 0 2 1
274 
+pintype=pwr
275 
+}
276 
+P 35000 39200 35300 39200 1 0 0
277 
+{
278 
+T 35200 39250 5 8 1 1 0 6 1
279 
+pinnumber=21
280 
+T 35200 39150 5 8 0 1 0 8 1
281 
+pinseq=21
282 
+T 35350 39200 9 8 1 1 0 0 1
283 
+pinlabel=AREF
284 
+T 35350 39200 5 8 0 1 0 2 1
285 
+pintype=in
286 
+}
287 
+P 35000 40000 35300 40000 1 0 0
288 
+{
289 
+T 35200 40050 5 8 1 1 0 6 1
290 
+pinnumber=10
291 
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292 
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293 
+T 35350 40000 9 8 1 1 0 0 1
294 
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295 
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296 
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297 
+}
298 
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299 
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300 
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301 
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302 
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303 
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304 
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305 
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306 
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307 
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308 
+}
309 
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310 
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311 
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312 
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313 
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314 
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315 
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316 
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317 
+pinlabel=PC6 (nRESET)
318 
+T 35350 41400 5 8 0 1 0 2 1
319 
+pintype=in
320 
+}
321 
+]
322 
+{
323 
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324 
+refdes=IC3
325 
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326 
+device=ATMEGA8
327 
+T 35300 42700 5 10 1 1 0 0 1
328 
+value=ATMEGA8
329 
+}
330 
+C 29300 38100 1 0 0 EMBEDDED7800.sym
331 
+[
332 
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344 
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2040 
+[
2041 
+L 42150 41000 42100 41050 3 0 0 0 -1 -1
2042 
+L 42175 41025 42125 41075 3 0 0 0 -1 -1
2043 
+L 42125 41000 42175 41000 3 0 0 0 -1 -1
2044 
+L 42175 41050 42175 41000 3 0 0 0 -1 -1
2045 
+L 42000 41100 42000 41200 3 0 0 0 -1 -1
2046 
+L 42000 41000 42000 40900 3 0 0 0 -1 -1
2047 
+L 42100 41000 41900 41000 3 0 0 0 -1 -1
2048 
+L 42100 41100 41900 41100 3 0 0 0 -1 -1
2049 
+L 42000 41000 41900 41100 3 0 0 0 -1 -1
2050 
+L 42100 41100 42000 41000 3 0 0 0 -1 -1
2051 
+P 42000 40700 42000 40900 1 0 0
2052 
+{
2053 
+T 42000 40700 5 10 0 0 270 0 1
2054 
+pintype=pas
2055 
+T 42050 40900 5 8 0 0 270 0 1
2056 
+pinseq=1
2057 
+T 42050 40900 5 8 0 1 270 0 1
2058 
+pinnumber=1
2059 
+}
2060 
+P 42000 41400 42000 41200 1 0 0
2061 
+{
2062 
+T 42000 41400 5 10 0 0 270 0 1
2063 
+pintype=pas
2064 
+T 42050 41300 5 8 0 0 270 0 1
2065 
+pinseq=2
2066 
+T 42050 41300 5 8 0 1 270 0 1
2067 
+pinnumber=2
2068 
+}
2069 
+T 41800 41050 8 10 0 1 270 5 1
2070 
+value=???
2071 
+T 42200 41050 8 10 0 1 270 3 1
2072 
+refdes=LED?
2073 
+T 42700 40800 5 10 0 0 270 0 1
2074 
+device=LED
2075 
+]
2076 
+{
2077 
+T 42700 40800 5 10 0 0 270 0 1
2078 
+device=LED
2079 
+T 41850 41200 5 10 1 1 0 6 1
2080 
+refdes=LED3
2081 
+T 41850 40900 5 10 1 1 0 8 1
2082 
+value=red 2mA
2083 
+}
2084 
+N 42000 40500 42000 40700 4
2085 
+N 42000 41400 42000 41600 4
2086 
+N 42000 41600 40900 41600 4
2087 
+N 38800 41600 40000 41600 4
2088 
+C 30300 39500 1 0 1 EMBEDDEDdiode.sym
2089 
+[
2090 
+T 29950 39600 8 10 0 1 0 5 1
2091 
+value=???
2092 
+T 29950 40000 8 10 0 1 0 3 1
2093 
+refdes=D?
2094 
+T 29700 40500 5 10 0 0 0 6 1
2095 
+device=diode
2096 
+L 30000 39800 30100 39800 3 0 0 0 -1 -1
2097 
+L 29900 39800 29800 39800 3 0 0 0 -1 -1
2098 
+L 29900 39900 29900 39700 3 0 0 0 -1 -1
2099 
+L 30000 39900 30000 39700 3 0 0 0 -1 -1
2100 
+L 29900 39800 30000 39700 3 0 0 0 -1 -1
2101 
+L 30000 39900 29900 39800 3 0 0 0 -1 -1
2102 
+P 29600 39800 29800 39800 1 0 0
2103 
+{
2104 
+T 29600 39800 5 10 0 0 0 6 1
2105 
+pintype=pas
2106 
+T 29800 39850 5 8 0 0 0 6 1
2107 
+pinseq=1
2108 
+T 29800 39850 5 8 0 1 0 6 1
2109 
+pinnumber=1
2110 
+}
2111 
+P 30300 39800 30100 39800 1 0 0
2112 
+{
2113 
+T 30300 39800 5 10 0 0 0 6 1
2114 
+pintype=pas
2115 
+T 30200 39850 5 8 0 0 0 6 1
2116 
+pinseq=2
2117 
+T 30200 39850 5 8 0 1 0 6 1
2118 
+pinnumber=2
2119 
+}
2120 
+]
2121 
+{
2122 
+T 29700 40500 5 10 0 0 0 6 1
2123 
+device=diode
2124 
+T 29950 40000 5 10 1 1 0 3 1
2125 
+refdes=D2
2126 
+T 29950 39600 5 10 1 1 0 5 1
2127 
+value=1N4004
2128 
+}
2129 
+N 29100 38800 29100 39800 4
2130 
+N 29100 39800 29600 39800 4
2131 
+N 30300 39800 30900 39800 4
2132 
+N 30900 39800 30900 38800 4
2133 
+C 33300 42600 1 0 0 EMBEDDEDvdd5.sym
2134 
+[
2135 
+T 33500 42900 8 10 0 1 0 3 1
2136 
+value=VDD5
2137 
+T 33600 42650 8 10 0 0 0 0 1
2138 
+net=VDD5:1
2139 
+L 33500 42750 33500 42700 3 0 0 0 -1 -1
2140 
+V 33500 42800 50 3 5 0 0 -1 -1 0 -1 -1 -1 -1 -1
2141 
+P 33500 42700 33500 42600 1 0 1
2142 
+{
2143 
+T 33500 42700 5 10 0 0 0 0 1
2144 
+pintype=pas
2145 
+T 33500 42800 3 6 0 0 0 0 1
2146 
+pinseq=1
2147 
+T 33500 42800 3 6 0 1 0 0 1
2148 
+pinnumber=1
2149 
+}
2150 
+]
2151 
+{
2152 
+T 33500 42900 5 10 1 1 0 3 1
2153 
+value=VDD5
2154 
+}
2155 
+C 34000 42600 1 0 0 EMBEDDEDvdd5.sym
2156 
+[
2157 
+T 34200 42900 8 10 0 1 0 3 1
2158 
+value=VDD5
2159 
+T 34300 42650 8 10 0 0 0 0 1
2160 
+net=VDD5:1
2161 
+L 34200 42750 34200 42700 3 0 0 0 -1 -1
2162 
+V 34200 42800 50 3 5 0 0 -1 -1 0 -1 -1 -1 -1 -1
2163 
+P 34200 42700 34200 42600 1 0 1
2164 
+{
2165 
+T 34200 42700 5 10 0 0 0 0 1
2166 
+pintype=pas
2167 
+T 34200 42800 3 6 0 0 0 0 1
2168 
+pinseq=1
2169 
+T 34200 42800 3 6 0 1 0 0 1
2170 
+pinnumber=1
2171 
+}
2172 
+]
2173 
+{
2174 
+T 34200 42900 5 10 1 1 0 3 1
2175 
+value=VDD5
2176 
+}
2177 
+C 40300 38100 1 270 0 EMBEDDEDcap.sym
2178 
+[
2179 
+L 40700 37700 40700 37800 3 0 0 0 -1 -1
2180 
+L 40700 37500 40700 37600 3 0 0 0 -1 -1
2181 
+L 40900 37600 40500 37600 3 0 0 0 -1 -1
2182 
+L 40900 37700 40500 37700 3 0 0 0 -1 -1
2183 
+P 40700 37300 40700 37500 1 0 0
2184 
+{
2185 
+T 40700 37300 5 10 0 0 270 0 1
2186 
+pintype=pas
2187 
+T 40750 37500 5 8 0 0 270 0 1
2188 
+pinseq=2
2189 
+T 40750 37500 5 8 0 1 270 0 1
2190 
+pinnumber=2
2191 
+}
2192 
+P 40700 38000 40700 37800 1 0 0
2193 
+{
2194 
+T 40700 38000 5 10 0 0 270 0 1
2195 
+pintype=pas
2196 
+T 40750 37900 5 8 0 0 270 0 1
2197 
+pinseq=1
2198 
+T 40750 37900 5 8 0 1 270 0 1
2199 
+pinnumber=1
2200 
+}
2201 
+T 40600 37500 8 10 0 1 270 2 1
2202 
+value=?F
2203 
+T 40600 37800 8 10 0 1 270 8 1
2204 
+refdes=C?
2205 
+T 40900 37800 5 10 0 0 270 0 1
2206 
+device=capacitor
2207 
+]
2208 
+{
2209 
+T 40900 37800 5 10 0 0 270 0 1
2210 
+device=capacitor
2211 
+T 40800 37800 5 10 1 1 0 0 1
2212 
+refdes=C11
2213 
+T 40800 37500 5 10 1 1 0 2 1
2214 
+value=10nF
2215 
+}
2216 
+N 40700 38000 40700 38200 4
2217 
+N 41700 37100 40700 37100 4
2218 
+N 40700 37100 40700 37300 4
2219 
+N 38800 41800 39300 41800 4
2220 
+N 39300 41800 39300 43400 4
2221 
+N 39300 43400 39800 43400 4
2222 
+N 42300 42700 42300 43700 4
2223 
+N 42300 43700 42500 43700 4
2224 
+C 43300 40000 1 270 0 EMBEDDEDres_pot.sym
2225 
+[
2226 
+L 43600 39500 43550 39450 3 0 0 0 -1 -1
2227 
+L 43600 39500 43550 39550 3 0 0 0 -1 -1
2228 
+L 43450 39500 43600 39500 3 0 0 0 -1 -1
2229 
+P 43300 39500 43450 39500 1 0 0
2230 
+{
2231 
+T 43300 39500 5 10 0 0 180 0 1
2232 
+pintype=pas
2233 
+T 43400 39450 5 8 0 0 180 0 1
2234 
+pinseq=2
2235 
+T 43350 39550 5 8 0 1 0 6 1
2236 
+pinnumber=2
2237 
+}
2238 
+B 43600 39150 200 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
2239 
+P 43700 40000 43700 39848 1 0 0
2240 
+{
2241 
+T 43700 40000 5 10 0 0 270 0 1
2242 
+pintype=pas
2243 
+T 43750 39900 5 8 0 0 270 0 1
2244 
+pinseq=1
2245 
+T 43750 39900 5 8 0 1 270 0 1
2246 
+pinnumber=1
2247 
+}
2248 
+P 43700 39000 43700 39150 1 0 0
2249 
+{
2250 
+T 43700 39000 5 10 0 0 270 0 1
2251 
+pintype=pas
2252 
+T 43750 39100 5 8 0 0 270 0 1
2253 
+pinseq=3
2254 
+T 43750 39100 5 8 0 1 270 0 1
2255 
+pinnumber=3
2256 
+}
2257 
+T 43550 39150 9 8 1 0 270 8 1
2258 
+R
2259 
+T 43550 39850 9 8 1 0 270 2 1
2260 
+L
2261 
+T 43900 39500 8 10 0 1 270 3 1
2262 
+value=?E
2263 
+T 44100 39500 8 10 0 1 270 3 1
2264 
+refdes=R?
2265 
+T 43650 39600 5 10 0 0 270 0 1
2266 
+device=resistor_potentiometer
2267 
+]
2268 
+{
2269 
+T 43650 39600 5 10 0 0 270 0 1
2270 
+device=resistor_potentiometer
2271 
+T 43900 39600 5 10 1 1 0 0 1
2272 
+refdes=R9
2273 
+T 43900 39500 5 10 1 1 0 2 1
2274 
+value=10kE
2275 
+}
2276 
+C 43500 40200 1 0 0 EMBEDDEDvdd5.sym
2277 
+[
2278 
+L 43700 40350 43700 40300 3 0 0 0 -1 -1
2279 
+V 43700 40400 50 3 5 0 0 -1 -1 0 -1 -1 -1 -1 -1
2280 
+P 43700 40300 43700 40200 1 0 1
2281 
+{
2282 
+T 43700 40400 3 6 0 1 0 0 1
2283 
+pinnumber=1
2284 
+T 43700 40400 3 6 0 0 0 0 1
2285 
+pinseq=1
2286 
+T 43700 40300 5 10 0 0 0 0 1
2287 
+pintype=pas
2288 
+}
2289 
+T 43700 40500 8 10 0 1 0 3 1
2290 
+value=VDD5
2291 
+T 43800 40250 8 10 0 0 0 0 1
2292 
+net=VDD5:1
2293 
+]
2294 
+{
2295 
+T 43700 40500 5 10 1 1 0 3 1
2296 
+value=VDD5
2297 
+}
2298 
+N 43700 40000 43700 40200 4
2299 
+C 43500 37800 1 0 0 EMBEDDEDgnd.sym
2300 
+[
2301 
+L 43600 38000 43800 38000 3 10 0 0 -1 -1
2302 
+P 43700 38000 43700 38200 1 0 1
2303 
+{
2304 
+T 43758 38061 5 4 0 1 0 0 1
2305 
+pinnumber=1
2306 
+T 43758 38061 5 4 0 0 0 0 1
2307 
+pinseq=1
2308 
+T 43700 38000 5 10 0 0 0 0 1
2309 
+pintype=pas
2310 
+}
2311 
+T 43700 37900 8 10 0 1 0 5 1
2312 
+value=GND
2313 
+T 43800 37850 8 10 0 0 0 0 1
2314 
+net=GND:1
2315 
+]
2316 
+{
2317 
+T 43700 37900 5 10 1 1 0 5 1
2318 
+value=GND
2319 
+}
2320 
+N 43700 38200 43700 39000 4
2321 
+N 42700 39300 42700 39500 4
2322 
+N 43700 38400 42700 38400 4
2323 
+N 42700 38400 42700 38600 4
2324 
+C 42300 39400 1 270 0 EMBEDDEDcap.sym
2325 
+[
2326 
+L 42700 39000 42700 39100 3 0 0 0 -1 -1
2327 
+L 42700 38800 42700 38900 3 0 0 0 -1 -1
2328 
+L 42900 38900 42500 38900 3 0 0 0 -1 -1
2329 
+L 42900 39000 42500 39000 3 0 0 0 -1 -1
2330 
+P 42700 38600 42700 38800 1 0 0
2331 
+{
2332 
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2333 
+pinnumber=2
2334 
+T 42750 38800 5 8 0 0 270 0 1
2335 
+pinseq=2
2336 
+T 42700 38600 5 10 0 0 270 0 1
2337 
+pintype=pas
2338 
+}
2339 
+P 42700 39300 42700 39100 1 0 0
2340 
+{
2341 
+T 42750 39200 5 8 0 1 270 0 1
2342 
+pinnumber=1
2343 
+T 42750 39200 5 8 0 0 270 0 1
2344 
+pinseq=1
2345 
+T 42700 39300 5 10 0 0 270 0 1
2346 
+pintype=pas
2347 
+}
2348 
+T 42600 38800 8 10 0 1 270 2 1
2349 
+value=?F
2350 
+T 42600 39100 8 10 0 1 270 8 1
2351 
+refdes=C?
2352 
+T 42900 39100 5 10 0 0 270 0 1
2353 
+device=capacitor
2354 
+]
2355 
+{
2356 
+T 42800 39100 5 10 1 1 0 0 1
2357 
+refdes=C12
2358 
+T 42800 38800 5 10 1 1 0 2 1
2359 
+value=10nF
2360 
+T 42900 39100 5 10 0 0 270 0 1
2361 
+device=capacitor
2362 
+}
2363 
+N 43300 39500 40000 39500 4
2364 
+N 40000 39500 40000 40200 4
2365 
+N 40000 40200 38800 40200 4
2366 
+T 43500 43600 9 10 1 0 0 0 1
2367 
+GROUND
2368 
+T 43500 44000 9 10 1 0 0 0 1
2369 
+FOCUS
2370 
+T 43500 43800 9 10 1 0 0 0 1
2371 
+SHUTTER
2372 
+T 41900 37500 9 10 1 0 0 0 2
2373 
+COARSE
2374 
+GRAINED
2375 
+T 43900 38800 9 10 1 0 0 0 2
2376 
+FINE
2377 
+GRAINED
time_trigger/firmware/.gitignore
View file @ a149600
... ... 
@@ -0,0 +1,4 @@
1 
+*.cof
2 
+*.hex
3 
+*.lst
4 
+*.obj
time_trigger/firmware/Makefile
View file @ a149600
... ... 
@@ -0,0 +1,50 @@
1 
+# time trigger for Olympus camera
2 
+# Copyright (C) 2013 Stefan Schuermans <stefan@blinkenarea.org>
3 
+# Copyleft: GNU public license - http://www.gnu.org/copyleft/gpl.html
4 
+# a BlinkenArea project - http://www.blinkenarea.org/
5 
+
6 
+NAME = time_trigger
7 
+DEVICE = m8
8 
+INC = m8def
9 
+LFUSE = 0xE1
10 
+HFUSE = 0xD9
11 
+LOCK = 0xC0
12 
+
13 
+PROGRAMMER = avrisp2
14 
+PROGRAMMER_PORT = usb
15 
+#PROGRAMMER = stk200
16 
+#PROGRAMMER_PORT = /dev/parport0
17 
+
18 
+BLINKENCONV = BlinkenConv
19 
+AVRA = avra
20 
+AVRDUDE = avrdude
21 
+
22 
+AVRDUDE_CALL = $(AVRDUDE) -c $(PROGRAMMER) -P $(PROGRAMMER_PORT) -p $(DEVICE)
23 
+
24 
+DATE = $(shell date +%Y-%m-%d)
25 
+YEAR = $(shell date +%Y)
26 
+PACKFILES = $(NAME).asm m8def.inc bml2inc.pl sig2inc.pl default.bml ChangeLog Makefile
27 
+FIRMWARE = $(NAME)-firmware-$(VER)_$(DATE)
28 
+PROG = $(NAME)-prog-$(VER)_$(DATE)
29 
+
30 
+.PHONY: all prog prog_fuses prog clean
31 
+.SUFFIXES:
32 
+.SECONDARY:
33 
+
34 
+all: $(NAME).hex
35 
+
36 
+$(NAME).hex: $(NAME).asm Makefile
37 
+	$(AVRA) -l $(NAME).lst $(NAME).asm
38 
+
39 
+prog_fuses: Makefile
40 
+	$(AVRDUDE_CALL) -u -e
41 
+	$(AVRDUDE_CALL) -u -U lfuse:w:$(LFUSE):m -U hfuse:w:$(HFUSE):m
42 
+
43 
+prog: $(NAME).hex Makefile
44 
+	$(AVRDUDE_CALL) -u -e
45 
+	$(AVRDUDE_CALL) -u -U flash:w:$(NAME).hex
46 
+	$(AVRDUDE_CALL) -u -V -U lock:w:$(LOCK):m
47 
+
48 
+clean:
49 
+	rm -f $(addprefix $(NAME)., lst obj cof hex eep.hex)
50 
+
time_trigger/firmware/m8def.inc
View file @ a149600
... ... 
@@ -0,0 +1,499 @@
1 
+;***************************************************************************
2 
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
3 
+;*
4 
+;* Number				:AVR000
5 
+;* File Name			:"m8def.inc"
6 
+;* Title				:Register/Bit Definitions for the ATmega8
7 
+;* Date                 :07.09.2001
8 
+;* Version              :1.00
9 
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
10 
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
11 
+;* Support E-mail		:avr@atmel.no
12 
+;* Target MCU			:ATmega8
13 
+;*
14 
+;* DESCRIPTION
15 
+;* When including this file in the assembly program file, all I/O register
16 
+;* names and I/O register bit names appearing in the data book can be used.
17 
+;* In addition, the six registers forming the three data pointers X, Y and
18 
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal
19 
+;* SRAM is also defined
20 
+;*
21 
+;* The Register names are represented by their hexadecimal address.
22 
+;*
23 
+;* The Register Bit names are represented by their bit number (0-7).
24 
+;*
25 
+;* Please observe the difference in using the bit names with instructions
26 
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
27 
+;* (skip if bit in register set/cleared). The following example illustrates
28 
+;* this:
29 
+;*
30 
+;* in	r16,PORTB				;read PORTB latch
31 
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
32 
+;* out  PORTB,r16				;output to PORTB
33 
+;*
34 
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
35 
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
36 
+;* rjmp	TOV0_is_set				;jump if set
37 
+;* ...							;otherwise do something else
38 
+;***************************************************************************
39 
+
40 
+;***** Specify Device
41 
+.device ATmega8
42 
+
43 
+;***** I/O Register Definitions
44 
+.equ	SREG	=$3f
45 
+.equ	SPH		=$3e
46 
+.equ	SPL		=$3d
47 
+.equ	GIMSK	=$3b
48 
+.equ	GICR	=$3b		; new name for GIMSK
49 
+.equ	GIFR	=$3a
50 
+.equ	TIMSK	=$39
51 
+.equ	TIFR	=$38
52 
+.equ	SPMCR	=$37
53 
+.equ    I2CR    =$36
54 
+.equ    TWCR    =$36
55 
+.equ    MCUCR   =$35
56 
+.equ    MCUSR   =$34		; For compatibility,
57 
+.equ    MCUCSR  =$34		; keep both names until further
58 
+.equ	TCCR0	=$33
59 
+.equ	TCNT0	=$32
60 
+.equ    OSCCAL  =$31
61 
+.equ    SFIOR   =$30
62 
+.equ	TCCR1A	=$2f
63 
+.equ	TCCR1B	=$2e
64 
+.equ	TCNT1H	=$2d
65 
+.equ	TCNT1L	=$2c
66 
+.equ	OCR1AH	=$2b
67 
+.equ	OCR1AL	=$2a
68 
+.equ	OCR1BH	=$29
69 
+.equ	OCR1BL	=$28
70 
+.equ	ICR1H	=$27
71 
+.equ	ICR1L	=$26
72 
+.equ	TCCR2	=$25
73 
+.equ	TCNT2	=$24
74 
+.equ	OCR2	=$23
75 
+.equ	ASSR	=$22
76 
+.equ	WDTCR	=$21
77 
+.equ    UBRRH   =$20		;  Note! UCSRC equals UBRRH
78 
+.equ	EEARH	=$1f
79 
+.equ	EEARL	=$1e
80 
+.equ	EEDR	=$1d
81 
+.equ	EECR	=$1c
82 
+.equ	PORTB	=$18
83 
+.equ	DDRB	=$17
84 
+.equ	PINB	=$16
85 
+.equ	PORTC	=$15
86 
+.equ	DDRC	=$14
87 
+.equ	PINC	=$13
88 
+.equ	PORTD	=$12
89 
+.equ	DDRD	=$11
90 
+.equ	PIND	=$10
91 
+.equ	SPDR	=$0f
92 
+.equ	SPSR	=$0e
93 
+.equ	SPCR	=$0d
94 
+.equ	UDR	=$0c
95 
+.equ	UCSRA	=$0b
96 
+.equ	UCSRB	=$0a
97 
+.equ	UCSRC	=$20		;  Note! UCSRC equals UBRRH
98 
+.equ	UBRRL	=$09
99 
+.equ	ACSR	=$08
100 
+.equ    ADMUX   =$07
101 
+.equ    ADCSRA  =$06
102 
+.equ    ADCH    =$05
103 
+.equ    ADCL    =$04
104 
+.equ    I2DR    =$03
105 
+.equ    I2AR    =$02
106 
+.equ    I2SR    =$01
107 
+.equ    I2BR    =$00
108 
+.equ    TWDR    =$03
109 
+.equ    TWAR    =$02
110 
+.equ    TWSR    =$01
111 
+.equ    TWBR    =$00
112 
+
113 
+
114 
+
115 
+;***** Bit Definitions
116 
+;GICR  (former GIMSK)
117 
+.equ	INT1	=7
118 
+.equ	INT0	=6
119 
+.equ	IVSEL	=1		; interrupt vector select
120 
+.equ	IVCE	=0		; interrupt vector change enable
121 
+
122 
+;GIFR
123 
+.equ	INTF1	=7
124 
+.equ	INTF0	=6
125 
+
126 
+;TIMSK
127 
+.equ    TOIE0   =0
128 
+.equ    TOIE1   =2
129 
+.equ    OCIE1B  =3
130 
+.equ    OCIE1A  =4
131 
+.equ    TICIE1  =5
132 
+.equ    TOIE2   =6
133 
+.equ    OCIE2   =7
134 
+
135 
+;TIFR
136 
+.equ    TOV0    =0
137 
+.equ    TOV1    =2
138 
+.equ    OCF1B   =3
139 
+.equ    OCF1A   =4
140 
+.equ    ICF1    =5
141 
+.equ    TOV2    =6
142 
+.equ    OCF2    =7
143 
+
144 
+;SPMCR
145 
+.equ	SPMIE	=7
146 
+.equ	RWWSB	=6
147 
+.equ	RWWSRE	=4
148 
+.equ	BLBSET	=3
149 
+.equ	PGWRT	=2
150 
+.equ	PGERS	=1
151 
+.equ	SPMEN	=0
152 
+
153 
+;MCUCR
154 
+.equ    SE      =7
155 
+.equ    SM2     =6
156 
+.equ    SM1     =5
157 
+.equ    SM0     =4
158 
+.equ    ISC11   =3
159 
+.equ    ISC10   =2
160 
+.equ    ISC01   =1
161 
+.equ    ISC00   =0
162 
+
163 
+;MCUCSR
164 
+.equ    WDRF    =3
165 
+.equ    BORF    =2
166 
+.equ    EXTRF   =1
167 
+.equ    PORF    =0
168 
+
169 
+;TCCR0
170 
+.equ	CS02	=2
171 
+.equ	CS01	=1
172 
+.equ	CS00	=0
173 
+
174 
+;TCCR1A
175 
+.equ	COM1A1	=7
176 
+.equ	COM1A0	=6
177 
+.equ	COM1B1	=5
178 
+.equ	COM1B0	=4
179 
+.equ	FOC1A	=3
180 
+.equ	FOC1B	=2
181 
+.equ	PWM11	=1	; OBSOLETE! Use WGM11
182 
+.equ	PWM10	=0	; OBSOLETE! Use WGM10
183 
+.equ	WGM11	=1
184 
+.equ	WGM10	=0
185 
+;TCCR1B
186 
+.equ	ICNC1	=7
187 
+.equ	ICES1	=6
188 
+.equ	CTC11	=4	; OBSOLETE! Use WGM13
189 
+.equ	CTC10	=3	; OBSOLETE! Use WGM12
190 
+.equ	WGM13	=4
191 
+.equ	WGM12	=3
192 
+.equ	CTC1	=3		; Obsolete - Included for backward compatibility
193 
+.equ	CS12	=2
194 
+.equ	CS11	=1
195 
+.equ	CS10	=0
196 
+
197 
+;TCCR2
198 
+.equ	FOC2	=7
199 
+.equ    PWM2    =6	; OBSOLETE! Use WGM20
200 
+.equ	WGM20	=6
201 
+.equ    COM21   =5
202 
+.equ    COM20   =4
203 
+.equ    CTC2    =3	; OBSOLETE! Use WGM21
204 
+.equ	WGM21	=3
205 
+.equ    CS22    =2
206 
+.equ    CS21    =1
207 
+.equ    CS20    =0
208 
+
209 
+;SFIOR
210 
+.equ    ADHSM   =4
211 
+.equ    ACME    =3
212 
+.equ    PUD     =2
213 
+.equ	PSR2	=1
214 
+.equ	PSR10	=0
215 
+
216 
+;WDTCR
217 
+.equ	WDCE	=4
218 
+.equ	WDTOE	=4
219 
+.equ	WDE	=3
220 
+.equ	WDP2	=2
221 
+.equ	WDP1	=1
222 
+.equ	WDP0	=0
223 
+
224 
+;EECR
225 
+.equ    EERIE   =3
226 
+.equ	EEMWE	=2
227 
+.equ	EEWE	=1
228 
+.equ	EERE	=0
229 
+
230 
+;PORTB
231 
+.equ	PB7	=7
232 
+.equ	PB6	=6
233 
+.equ	PB5	=5
234 
+.equ	PB4	=4
235 
+.equ	PB3	=3
236 
+.equ	PB2	=2
237 
+.equ	PB1	=1
238 
+.equ	PB0	=0
239 
+
240 
+;DDRB
241 
+.equ	DDB7	=7
242 
+.equ	DDB6	=6
243 
+.equ	DDB5	=5
244 
+.equ	DDB4	=4
245 
+.equ	DDB3	=3
246 
+.equ	DDB2	=2
247 
+.equ	DDB1	=1
248 
+.equ	DDB0	=0
249 
+
250 
+;PINB
251 
+.equ	PINB7	=7
252 
+.equ	PINB6	=6
253 
+.equ	PINB5	=5
254 
+.equ	PINB4	=4
255 
+.equ	PINB3	=3
256 
+.equ	PINB2	=2
257 
+.equ	PINB1	=1
258 
+.equ	PINB0	=0
259 
+
260 
+;PORTC
261 
+.equ	PC6	=6
262 
+.equ	PC5	=5
263 
+.equ	PC4	=4
264 
+.equ	PC3	=3
265 
+.equ	PC2	=2
266 
+.equ	PC1	=1
267 
+.equ	PC0	=0
268 
+
269 
+;DDRC
270 
+.equ	DDC6	=6
271 
+.equ	DDC5	=5
272 
+.equ	DDC4	=4
273 
+.equ	DDC3	=3
274 
+.equ	DDC2	=2
275 
+.equ	DDC1	=1
276 
+.equ	DDC0	=0
277 
+
278 
+;PINC
279 
+.equ	PINC6	=6
280 
+.equ	PINC5	=5
281 
+.equ	PINC4	=4
282 
+.equ	PINC3	=3
283 
+.equ	PINC2	=2
284 
+.equ	PINC1	=1
285 
+.equ	PINC0	=0
286 
+
287 
+;PORTD
288 
+.equ	PD7	=7
289 
+.equ	PD6	=6
290 
+.equ	PD5	=5
291 
+.equ	PD4	=4
292 
+.equ	PD3	=3
293 
+.equ	PD2	=2
294 
+.equ	PD1	=1
295 
+.equ	PD0	=0
296 
+
297 
+;DDRD
298 
+.equ	DDD7	=7
299 
+.equ	DDD6	=6
300 
+.equ	DDD5	=5
301 
+.equ	DDD4	=4
302 
+.equ	DDD3	=3
303 
+.equ	DDD2	=2
304 
+.equ	DDD1	=1
305 
+.equ	DDD0	=0
306 
+
307 
+;PIND
308 
+.equ	PIND7	=7
309 
+.equ	PIND6	=6
310 
+.equ	PIND5	=5
311 
+.equ	PIND4	=4
312 
+.equ	PIND3	=3
313 
+.equ	PIND2	=2
314 
+.equ	PIND1	=1
315 
+.equ	PIND0	=0
316 
+
317 
+;UCSRA
318 
+.equ	RXC	=7
319 
+.equ	TXC	=6
320 
+.equ	UDRE	=5
321 
+.equ	FE	=4
322 
+;.equ    OR      =3              ; old name kept for compatibilty
323 
+.equ	DOR	=3
324 
+.equ	UPE	=2
325 
+.equ	PE	=2
326 
+.equ	U2X	=1
327 
+.equ	MPCM	=0
328 
+
329 
+;UCSRB
330 
+.equ	RXCIE	=7
331 
+.equ	TXCIE	=6
332 
+.equ	UDRIE	=5
333 
+.equ	RXEN	=4
334 
+.equ	TXEN	=3
335 
+.equ	CHR9	=2		; old name kept for compatibilty
336 
+.equ	UCSZ2	=2
337 
+.equ	RXB8	=1
338 
+.equ	TXB8	=0
339 
+
340 
+;UCSRC
341 
+.equ	URSEL	=7
342 
+.equ	UMSEL	=6
343 
+.equ	UPM1	=5
344 
+.equ	UPM0	=4
345 
+.equ	USBS	=3
346 
+.equ	UCSZ1	=2
347 
+.equ	UCSZ0	=1
348 
+.equ	UCPOL	=0
349 
+
350 
+;SPCR
351 
+.equ	SPIE	=7
352 
+.equ	SPE	=6
353 
+.equ	DORD	=5
354 
+.equ	MSTR	=4
355 
+.equ	CPOL	=3
356 
+.equ	CPHA	=2
357 
+.equ	SPR1	=1
358 
+.equ	SPR0	=0
359 
+
360 
+;SPSR
361 
+.equ	SPIF	=7
362 
+.equ	WCOL	=6
363 
+.equ	SPI2X	=0
364 
+
365 
+;ACSR
366 
+.equ	ACD	=7
367 
+.equ    ACBG    =6
368 
+.equ	ACO	=5
369 
+.equ	ACI	=4
370 
+.equ	ACIE	=3
371 
+.equ	ACIC	=2
372 
+.equ	ACIS1	=1
373 
+.equ	ACIS0	=0
374 
+
375 
+;ADMUX
376 
+.equ    REFS1   =7
377 
+.equ    REFS0   =6
378 
+.equ    ADLAR   =5
379 
+.equ    MUX3    =3
380 
+.equ    MUX2    =2
381 
+.equ    MUX1    =1
382 
+.equ    MUX0    =0
383 
+
384 
+;ADCSR
385 
+.equ    ADEN    =7
386 
+.equ    ADSC    =6
387 
+.equ    ADFR    =5
388 
+.equ    ADIF    =4
389 
+.equ    ADIE    =3
390 
+.equ    ADPS2   =2
391 
+.equ    ADPS1   =1
392 
+.equ    ADPS0   =0
393 
+
394 
+; TWCR
395 
+.equ    TWINT   =7
396 
+.equ    TWEA    =6
397 
+.equ    TWSTA   =5
398 
+.equ    TWSTO   =4
399 
+.equ    TWWC    =3
400 
+.equ    TWEN    =2
401 
+
402 
+.equ    TWIE    =0
403 
+
404 
+; TWAR
405 
+.equ    TWA6    =7
406 
+.equ    TWA5    =6
407 
+.equ    TWA4    =5
408 
+.equ    TWA3    =4
409 
+.equ    TWA2    =3
410 
+.equ    TWA1    =2
411 
+.equ    TWA0    =1
412 
+.equ    TWGCE   =0
413 
+
414 
+; TWSR
415 
+.equ    TWS7    =7
416 
+.equ    TWS6    =6
417 
+.equ    TWS5    =5
418 
+.equ    TWS4    =4
419 
+.equ    TWS3    =3
420 
+.equ	TWPS1	=1
421 
+.equ	TWPS0	=0
422 
+
423 
+;ASSR
424 
+.equ    AS2     =3
425 
+.equ    TCN2UB  =2
426 
+.equ    OCR2UB  =1
427 
+.equ    TCR2UB  =0
428 
+
429 
+.def	XL	=r26
430 
+.def	XH	=r27
431 
+.def	YL	=r28
432 
+.def	YH	=r29
433 
+.def	ZL	=r30
434 
+.def	ZH	=r31
435 
+
436 
+.equ 	RAMEND =$45F
437 
+.equ	FLASHEND =$FFF
438 
+
439 
+						;  byte groups
440 
+						;  /\/--\/--\/--\
441 
+.equ 	SMALLBOOTSTART	=0b00111110000000  ;($0F80) smallest boot block is 256
442 
+.equ 	SECONDBOOTSTART	=0b00111100000000  ;($0F00) 2'nd boot block size is 512
443 
+.equ 	THIRDBOOTSTART	=0b00111000000000  ;($0E00) third boot block size is 1K
444 
+.equ 	LARGEBOOTSTART	=0b00110000000000  ;($0C00) largest boot block is 2K
445 
+.equ 	BOOTSTART		=THIRDBOOTSTART  ;OBSOLETE!!! kept for compatibility
446 
+.equ	PAGESIZE		=32     ;number of WORDS in a page
447 
+
448 
+.equ	INT0addr=$001	; External Interrupt0 Vector Address
449 
+.equ	INT1addr=$002	; External Interrupt1 Vector Address
450 
+.equ	OC2addr =$003	; Output Compare2 Interrupt Vector Address
451 
+.equ	OVF2addr=$004	; Overflow2 Interrupt Vector Address
452 
+.equ	ICP1addr=$005	; Input Capture1 Interrupt Vector Address
453 
+.equ	OC1Aaddr=$006	; Output Compare1A Interrupt Vector Address
454 
+.equ	OC1Baddr=$007	; Output Compare1B Interrupt Vector Address
455 
+.equ	OVF1addr=$008	; Overflow1 Interrupt Vector Address
456 
+.equ	OVF0addr=$009	; Overflow0 Interrupt Vector Address
457 
+.equ	SPIaddr =$00a	; SPI Interrupt Vector Address
458 
+.equ	URXCaddr=$00b	; USART Receive Complete Interrupt Vector Address
459 
+.equ	UDREaddr=$00c	; USART Data Register Empty Interrupt Vector Address
460 
+.equ	UTXCaddr=$00d	; USART Transmit Complete Interrupt Vector Address
461 
+.equ	ADCCaddr=$00e	; ADC Interrupt Vector Address
462 
+.equ	ERDYaddr=$00f	; EEPROM Interrupt Vector Address
463 
+.equ	ACIaddr =$010	; Analog Comparator Interrupt Vector Address
464 
+.equ    TWIaddr =$011   ; Irq. vector address for Two-Wire Interface
465 
+.equ	SPMaddr =$012	; SPM complete Interrupt Vector Address
466 
+.equ	SPMRaddr =$012	; SPM complete Interrupt Vector Address
467 
+
468 
+
469 
+; constants for TWSR status
470 
+.equ TW_STATUS_MASK = 0xF8
471 
+.equ TW_START = 0x08 ; start condition transmitted
472 
+.equ TW_REP_START = 0x10 ; repeated start condition transmitted
473 
+.equ TW_MT_SLA_ACK = 0x18 ; SLA+W transmitted, ACK received
474 
+.equ TW_MT_SLA_NACK = 0x20 ; SLA+W transmitted, NACK received
475 
+.equ TW_MT_DATA_ACK = 0x28 ; data transmitted, ACK received
476 
+.equ TW_MT_DATA_NACK = 0x30 ; data transmitted, NACK received
477 
+.equ TW_MT_ARB_LOST = 0x38 ; arbitration lost in SLA+W or data
478 
+.equ TW_MR_ARB_LOST = 0x38 ; arbitration lost in SLA+R or NACK
479 
+.equ TW_MR_SLA_ACK = 0x40 ; SLA+R transmitted, ACK received
480 
+.equ TW_MR_SLA_NACK = 0x48 ; SLA+R transmitted, NACK received
481 
+.equ TW_MR_DATA_ACK = 0x50 ; data received, ACK returned
482 
+.equ TW_MR_DATA_NACK = 0x58 ; data received, NACK returned
483 
+.equ TW_ST_SLA_ACK = 0xA8 ; SLA+R received, ACK returned
484 
+.equ TW_ST_ARB_LOST_SLA_ACK = 0xB0 ; arbitration lost in SLA+RW, SLA+R received, ACK returned
485 
+.equ TW_ST_DATA_ACK = 0xB8 ; data transmitted, ACK received
486 
+.equ TW_ST_DATA_NACK = 0xC0 ; data transmitted, NACK received
487 
+.equ TW_ST_LAST_DATA = 0xC8 ; last data byte transmitted, ACK received
488 
+.equ TW_SR_SLA_ACK = 0x60 ; SLA+W received, ACK returned
489 
+.equ TW_SR_ARB_LOST_SLA_ACK = 0x68 ; arbitration lost in SLA+RW, SLA+W received, ACK returned
490 
+.equ TW_SR_GCALL_ACK = 0x70 ; general call received, ACK returned
491 
+.equ TW_SR_ARB_LOST_GCALL_ACK = 0x78 ; arbitration lost in SLA+RW, general call received, ACK returned
492 
+.equ TW_SR_DATA_ACK = 0x80 ; data received, ACK returned
493 
+.equ TW_SR_DATA_NACK = 0x88 ; data received, NACK returned
494 
+.equ TW_SR_GCALL_DATA_ACK = 0x90 ; general call data received, ACK returned
495 
+.equ TW_SR_GCALL_DATA_NACK = 0x98 ; general call data received, NACK returned
496 
+.equ TW_SR_STOP = 0xA0 ; stop or repeated start condition received while selected
497 
+.equ TW_NO_INFO = 0xF8 ; no state information available
498 
+.equ TW_BUS_ERROR = 0x00 ; illegal start or stop condition
499 
+
time_trigger/firmware/time_trigger.asm
View file @ a149600
... ... 
@@ -0,0 +1,224 @@
1 
+; time trigger for Olympus camera
2 
+; Copyright (C) 2013 Stefan Schuermans <stefan@blinkenarea.org>
3 
+; Copyleft: GNU public license - http://www.gnu.org/copyleft/gpl.html
4 
+; a BlinkenArea project - http://www.blinkenarea.org/
5 
+
6 
+
7 
+
8 
+; 1 MHz internal RC oscillator
9 
+
10 
+
11 
+
12 
+.INCLUDE        "m8def.inc"
13 
+
14 
+
15 
+
16 
+; IO pins
17 
+.equ    PORT_LED        =       PORTB
18 
+.equ    BIT_LED         =       1
19 
+.equ    PORT_CAM        =       PORTB
20 
+.equ    BIT_CAM         =       2
21 
+
22 
+
23 
+
24 
+; multiplication results
25 
+.def    MUL_RES_L       =       r0
26 
+.def    MUL_RES_H       =       r1
27 
+
28 
+
29 
+
30 
+; general purpose registers
31 
+.def    DATA_L          =       r16
32 
+.def    DATA_H          =       r17
33 
+.def    TMP             =       r18
34 
+.def    CNT             =       r19
35 
+
36 
+
37 
+
38 
+.DSEG
39 
+.ORG    0x060
40 
+
41 
+
42 
+
43 
+.CSEG
44 
+.ORG    0x000
45 
+        rjmp    ENTRY                           ; RESET
46 
+        reti                                    ; INT0
47 
+        reti                                    ; INT1
48 
+        reti                                    ; TIMER2_COMP
49 
+        reti                                    ; TIMER2_OVF
50 
+        reti                                    ; TIMER1_CAPT
51 
+        reti                                    ; TIMER1_COMPA
52 
+        reti                                    ; TIMER1_COMPB
53 
+        reti                                    ; TIMER1_OVF
54 
+        reti                                    ; TIMER0_OVF
55 
+        reti                                    ; SPI_STC
56 
+        reti                                    ; USART_RXC
57 
+        reti                                    ; USART_UDRE
58 
+        reti                                    ; USART_TXC
59 
+        reti                                    ; ADC
60 
+        reti                                    ; EE_RDY
61 
+        reti                                    ; ANA_COMP
62 
+        reti                                    ; TWI
63 
+        reti                                    ; SPM_RDY
64 
+
65 
+
66 
+
67 
+; code entry point
68 
+ENTRY:
69 
+; initialize stack pointer
70 
+        ldi     TMP,HIGH(RAMEND)
71 
+        out     SPH,TMP
72 
+        ldi     TMP,LOW(RAMEND)
73 
+        out     SPL,TMP
74 
+; enable watchdog (64ms)
75 
+        wdr
76 
+        ldi     TMP,1<<WDCE|1<<WDE
77 
+        out     WDTCR,TMP
78 
+        ldi     TMP,1<<WDE|1<<WDP1
79 
+        out     WDTCR,TMP
80 
+        wdr
81 
+; setup I/O pins
82 
+;   o = output, low
83 
+;   O = output, high
84 
+;   i = input, pull-up disabled
85 
+;   I = input, pull-up enabled
86 
+;   . = pin not available
87 
+        ldi     TMP,0xE0                        ; PB: IIIooooo
88 
+        out     PORTB,TMP
89 
+        ldi     TMP,0x1F
90 
+        out     DDRB,TMP
91 
+        ldi     TMP,0x00                        ; PC: ..ooooii
92 
+        out     PORTC,TMP
93 
+        ldi     TMP,0x3C
94 
+        out     DDRC,TMP
95 
+        ldi     TMP,0x00                        ; PD: iioooooo
96 
+        out     PORTD,TMP
97 
+        ldi     TMP,0x3F
98 
+        out     DDRD,TMP
99 
+; enable analog comparator
100 
+        ldi     TMP,0                           ; positive input: AIN0
101 
+        out     ACSR,TMP
102 
+        in      TMP,SFIOR                       ; negative input: AIN1
103 
+        cbr     TMP,1<<ACME
104 
+        out     SFIOR,TMP
105 
+; enable analaog to digital converter
106 
+        ldi     TMP,1<<REFS0                    ; AREF = AVCC, select ADC0
107 
+        out     ADMUX,TMP
108 
+        ldi     TMP,1<<ADEN|1<<ADPS1|1<<ADPS0   ; enable, clock 1:8
109 
+        out     ADCSRA,TMP
110 
+; jump to main program
111 
+        rjmp    MAIN
112 
+
113 
+
114 
+
115 
+; wait CNT milliseconds (CNT = 0 -> wait 256ms)
116 
+WAIT_MS:
117 
+        ldi     TMP,250                         ; wait 1ms
118 
+WAIT_MS_INNER:
119 
+        wdr
120 
+        dec     TMP
121 
+        brne    WAIT_MS_INNER                   ; wait 1ms - bottom
122 
+        dec     CNT
123 
+        brne    WAIT_MS                         ; outer loop bottom
124 
+        ret                                     ; done
125 
+
126 
+
127 
+
128 
+; wait CNT * 25us (CNT = 0 -> wait 6400us)
129 
+WAIT_25US:
130 
+        ldi     TMP,5                           ; wait 25us
131 
+WAIT_25US_INNER:
132 
+        wdr
133 
+        dec     TMP
134 
+        brne    WAIT_25US_INNER                 ; wait 25us - bottom
135 
+        dec     CNT
136 
+        brne    WAIT_25US                       ; outer loop bottom
137 
+        ret                                     ; done
138 
+
139 
+
140 
+
141 
+; main program - initialization
142 
+MAIN:
143 
+        wdr                                     ; watchdog reset
144 
+        cbi     PORT_LED,BIT_LED                ; LED off
145 
+        cbi     PORT_CAM,BIT_CAM                ; camera trigger off
146 
+
147 
+; main program - main loop
148 
+MAIN_LOOP:
149 
+
150 
+; wait for trigger
151 
+MAIN_WAIT_LOW:                                  ; wait for comperator out low
152 
+        wdr
153 
+        sbic    ACSR,ACO
154 
+        rjmp    MAIN_WAIT_LOW
155 
+MAIN_WAIT_HIGH:                                 ; wait for comperator out high
156 
+        wdr
157 
+        sbis    ACSR,ACO
158 
+        rjmp    MAIN_WAIT_HIGH
159 
+
160 
+; read configured coarse-grained time
161 
+        ldi     TMP,1<<REFS0                    ; AREF = AVCC, select ADC0
162 
+        out     ADMUX,TMP
163 
+        sbi     ADCSRA,ADSC                     ; start A/D conversion
164 
+MAIN_C_WAIT_ADC:                                ; wait for A/C conv to finish
165 
+        sbic    ADCSRA,ADSC
166 
+        rjmp    MAIN_C_WAIT_ADC
167 
+
168 
+; LED on
169 
+        sbi     PORT_LED,BIT_LED
170 
+
171 
+; wait for configured coarse-grained time
172 
+        in      DATA_L,ADCL                     ; read ADC
173 
+        in      DATA_H,ADCH
174 
+MAIN_C_WAIT_H:                                  ; wait ADCH * 256ms
175 
+        cpi     DATA_H,0                        ;   check if high part 0
176 
+        breq    MAIN_C_WAIT_H_END
177 
+        ldi     CNT,0                           ;   wait 256ms
178 
+        rcall   WAIT_MS
179 
+        dec     DATA_H                          ;   decrement high part
180 
+        rjmp    MAIN_C_WAIT_H                   ;   bottom of loop
181 
+MAIN_C_WAIT_H_END:                              ; wait ADCL * 1ms
182 
+        cpi     DATA_L,0                        ;   check if low part 0
183 
+        breq    MAIN_C_WAIT_L_END
184 
+        mov     CNT,DATA_L
185 
+        rcall   WAIT_MS
186 
+MAIN_C_WAIT_L_END:
187 
+
188 
+; read configured fine-grained time
189 
+        ldi     TMP,1<<REFS0|1<<MUX0            ; AREF = AVCC, select ADC1
190 
+        out     ADMUX,TMP
191 
+        sbi     ADCSRA,ADSC                     ; start A/D conversion
192 
+MAIN_F_WAIT_ADC:                                ; wait for A/C conv to finish
193 
+        sbic    ADCSRA,ADSC
194 
+        rjmp    MAIN_F_WAIT_ADC
195 
+
196 
+; wait for configured fine-grained time
197 
+        in      DATA_L,ADCL                     ; read ADC
198 
+        in      DATA_H,ADCH
199 
+MAIN_F_WAIT_H:                                  ; wait ADCH * 6400us
200 
+        cpi     DATA_H,0                        ;   check if high part 0
201 
+        breq    MAIN_F_WAIT_H_END
202 
+        ldi     CNT,0                           ;   wait 256ms
203 
+        rcall   WAIT_25US
204 
+        dec     DATA_H                          ;   decrement high part
205 
+        rjmp    MAIN_F_WAIT_H                   ;   bottom of loop
206 
+MAIN_F_WAIT_H_END:                              ; wait ADCL * 25us
207 
+        cpi     DATA_L,0                        ;   check if low part 0
208 
+        breq    MAIN_F_WAIT_L_END
209 
+        mov     CNT,DATA_L
210 
+        rcall   WAIT_25US
211 
+MAIN_F_WAIT_L_END:
212 
+
213 
+; LED off
214 
+        cbi     PORT_LED,BIT_LED
215 
+
216 
+; output camera trigger
217 
+        sbi     PORT_CAM,BIT_CAM                ; camera trigger on
218 
+        ldi     CNT,200                         ; wait 200ms
219 
+        rcall   WAIT_MS
220 
+        cbi     PORT_CAM,BIT_CAM                ; camera trigger off
221 
+
222 
+; bottom of main loop
223 
+        rjmp    MAIN_LOOP
224 
+
0 225