MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
progmem 8KB -> 16KB
d1693e8 @ 2012-03-24 19:04:32
| blocks | improve synchonous FIFO implementation (get rid of delays between reads) | 2012-03-11 18:59:11 |
|---|---|---|
| constraints | adapt ethernet TX clock timing constraint to transmission of data on falling edge | 2012-03-07 21:18:54 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | progmem 8KB -> 16KB | 2012-03-24 19:04:32 |
| io | handle eth TX packets of odd size in HW | 2012-03-24 17:30:33 |
| mips | fix divider (result) | 2012-03-21 22:11:20 |
| stuff | remove old exmaple packets | 2012-03-24 14:06:47 |
| system | progmem 8KB -> 16KB | 2012-03-24 19:04:32 |
| test | implemented IP + ICMP, fixed ARP (padding overwriting stack) | 2012-03-24 13:58:46 |
| .gitignore | migration to Xilinx 13.4 | 2012-03-24 14:06:11 |
| Default.wcfg | migration to Xilinx 13.4 | 2012-03-24 14:06:11 |
| mips_sys.ipf | migration to Xilinx 13.4 | 2012-03-24 14:06:11 |
| mips_sys.xise | migration to Xilinx 13.4 | 2012-03-24 14:06:11 |