MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans implemented ethernet RX busmaster -> packet reception working c906a48 @ 2012-03-03 23:42:55
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.gitignore some links to MIPS ISA documentation 2012-01-23 22:11:08
urls some links to MIPS ISA documentation 2012-01-23 22:11:08