MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
65b2622 @ 2012-02-21 20:40:30
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| testbed.vhd | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |