MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
fix reading (1 cycle latency) from ethernet peripheral
3189179 @ 2012-02-26 18:26:02
| .. | ||
|---|---|---|
| crc32.vhd | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
| fifo.vhd | added FIFO to UART TX | 2012-02-20 13:00:00 |
| rwram.vhd | added FIFO to UART TX | 2012-02-20 13:00:00 |