MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing 1f34390 @ 2012-03-10 10:50:55
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.gitignore some links to MIPS ISA documentation 2012-01-23 22:11:08
urls some links to MIPS ISA documentation 2012-01-23 22:11:08