LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY e_io_leds IS
    PORT (
        rst:        IN  std_logic;
        clk:        IN  std_logic;
        o_rd_data:  OUT std_logic_vector(7 DOWNTO 0);
        i_wr_data:  IN  std_logic_vector(7 DOWNTO 0);
        i_wr_en:    IN  std_logic;
        pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
    );
END ENTITY e_io_leds;

ARCHITECTURE a_io_leds OF e_io_leds IS

    SIGNAL n_leds: std_logic_vector(7 DOWNTO 0);
    SIGNAL r_leds: std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');

BEGIN

    p_next: PROCESS(r_leds, i_wr_data, i_wr_en)
    BEGIN
        IF i_wr_en = '1' THEN
            n_leds <= i_wr_data;
        ELSE
            n_leds <= r_leds;
        END IF;
    END PROCESS p_next;

    p_sync: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_leds <= (OTHERS => '0');
        ELSIF rising_edge(clk) THEN
            r_leds <= n_leds;
        END IF;
    END PROCESS p_sync;

    p_read: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            o_rd_data <= (OTHERS => '0');
        ELSIF rising_edge(clk) THEN
            o_rd_data <= r_leds;
        END IF;
    END PROCESS p_read;

    pin_o_leds <= r_leds;

END ARCHITECTURE a_io_leds;