LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;

ENTITY e_mips_cmp IS
    PORT (
        i_cmp: IN  t_cmp;
        i_op1: IN  std_logic_vector(31 DOWNTO 0);
        i_op2: IN  std_logic_vector(31 DOWNTO 0);
        o_res: OUT std_logic
    );
END ENTITY e_mips_cmp;

ARCHITECTURE a_mips_cmp OF e_mips_cmp IS

BEGIN

    p_cmp: PROCESS(i_cmp, i_op1, i_op2)
        VARIABLE v_op1_s: signed(31 DOWNTO 0);
        VARIABLE v_op2_s: signed(31 DOWNTO 0);
        VARIABLE v_res: boolean;
    BEGIN
        v_op1_s := signed(i_op1);
        v_op2_s := signed(i_op2);
        CASE i_cmp IS
            WHEN cmp_eq => v_res := i_op1 = i_op2;
            WHEN cmp_gez => v_res := v_op1_s >= 0;
            WHEN cmp_gtz => v_res := v_op1_s > 0;
            WHEN cmp_lez => v_res := v_op1_s <= 0;
            WHEN cmp_ltz => v_res := v_op1_s < 0;
            WHEN cmp_ne => v_res := i_op1 /= i_op2;
            WHEN OTHERS => v_res := false;
        END CASE;
        IF v_res THEN
            o_res <= '1';
        ELSE
            o_res <= '0';
        END IF;
    END PROCESS p_cmp;

END ARCHITECTURE a_mips_cmp;