LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY e_block_crc32 IS
    PORT (
        rst:     IN  std_logic;
        clk:     IN  std_logic;
        i_en:    IN  std_logic;
        i_start: IN  std_logic;
        i_data:  IN  std_logic_vector( 7 DOWNTO 0);
        o_crc:   OUT std_logic_vector(31 DOWNTO 0)
    );
END ENTITY e_block_crc32;

ARCHITECTURE a_block_crc32 OF e_block_crc32 IS

    TYPE t_xor IS ARRAY(7 DOWNTO 0) of std_logic_vector(31 DOWNTO 0);

    CONSTANT c_xor: t_xor := (0 => X"77073096",
                              1 => X"EE0E612C",
                              2 => X"076DC419",
                              3 => X"0EDB8832",
                              4 => X"1DB71064",
                              5 => X"3B6E20C8",
                              6 => X"76DC4190",
                              7 => X"EDB88320");

    SIGNAL r_crc: std_logic_vector(31 DOWNTO 0) := X"FFFFFFFF";
    SIGNAL n_crc: std_logic_vector(31 DOWNTO 0);

BEGIN

    p_next: PROCESS(r_crc, i_en, i_start, i_data)
        VARIABLE v_crc:  std_logic_vector(31 DOWNTO 0);
        VARIABLE v_bits: std_logic_vector( 7 DOWNTO 0);
    BEGIN
        v_crc := r_crc;
        IF i_en = '1' THEN
            IF i_start = '1' THEN
                v_crc := X"FFFFFFFF";
            END IF;
            v_bits := v_crc(7 DOWNTO 0) XOR i_data;
            v_crc  := X"00" & v_crc(31 DOWNTO 8);
            FOR i IN 7 DOWNTO 0 LOOP
                IF v_bits(i) = '1' THEN
                    v_crc := v_crc XOR c_xor(i);
                END IF;
            END LOOP;
        END IF;
        n_crc <= v_crc;
    END PROCESS p_next;

    p_sync: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_crc <= X"FFFFFFFF";
        ELSIF rising_edge(clk) THEN
            r_crc <= n_crc;
        END IF;
    END PROCESS p_sync;

    o_crc <= r_crc XOR X"FFFFFFFF";

END ARCHITECTURE a_block_crc32;