LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.textio.all;

ENTITY e_testbed IS
END ENTITY e_testbed;

ARCHITECTURE a_testbed OF e_testbed IS

    COMPONENT e_system IS
        PORT (
            rst:          IN  std_logic;
            clk:          IN  std_logic;
            i_core_stall: IN  std_logic;
            i_prg_addr:   IN  std_logic_vector(31 DOWNTO 0);
            i_prg_data:   IN  std_logic_vector(31 DOWNTO 0);
            i_prg_en:     IN  std_logic;
            o_dummy:      OUT std_logic_vector(31 DOWNTO 0)
        );
    END COMPONENT e_system;

    SIGNAL s_rst:        std_logic;
    SIGNAL s_clk:        std_logic;
    SIGNAL s_core_stall: std_logic;
    SIGNAL s_prg_addr:   std_logic_vector(31 DOWNTO 0);
    SIGNAL s_prg_data:   std_logic_vector(31 DOWNTO 0);
    SIGNAL s_prg_en:     std_logic;
    SIGNAL s_dummy:      std_logic_vector(31 DOWNTO 0);

BEGIN

    system: e_system
        PORT MAP (
            clk          => s_clk,
            rst          => s_rst,
            i_core_stall => s_core_stall,
            i_prg_addr   => s_prg_addr,
            i_prg_data   => s_prg_data,
            i_prg_en     => s_prg_en,
            o_dummy      => s_dummy
        );

    p_rst_clk: PROCESS
        FILE     f_data:  text IS "fw/fw.dat";
        VARIABLE v_line:  line;
        VARIABLE v_addr:  integer;
        VARIABLE v_data1: integer;
        VARIABLE v_data2: integer;
    BEGIN
        s_rst        <= '0';
        s_clk        <= '0';
        s_core_stall <= '1';
        s_prg_addr   <= (OTHERS => '0');
        s_prg_data   <= (OTHERS => '0');
        s_prg_en     <= '0';

        WAIT FOR 1 ps;
        s_rst <= '1';
        WAIT FOR 1 ps;
        s_rst <= '0';

        s_prg_en <= '1';
        v_addr   := 0;
        WHILE NOT endfile(f_data) LOOP
            readline(f_data, v_line);
            read(v_line, v_data1);
            read(v_line, v_data2);
            s_prg_addr <= std_logic_vector(to_unsigned(v_addr, 32));
            s_prg_data <= std_logic_vector(to_unsigned(v_data2, 16)) &
                          std_logic_vector(to_unsigned(v_data1, 16));
            WAIT FOR 1 ps;
            s_clk <= '1';
            WAIT FOR 1 ps;
            s_clk <= '0';
            v_addr := v_addr + 4;
        END LOOP;
        s_prg_en <= '0';

        WAIT FOR 10 ns;
        s_rst <= '1';
        WAIT FOR 10 ns;
        s_rst <= '0';

        s_core_stall <= '0';
        WHILE TRUE LOOP
            WAIT FOR 10 ns;
            s_clk <= '1';
            WAIT FOR 10 ns;
            s_clk <= '0';
        END LOOP;
    END PROCESS p_rst_clk;

END ARCHITECTURE a_testbed;