LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY e_ram IS
    GENERIC (
        addr_width: natural;
        data_width: natural
    );
    PORT (
        clk:       IN  std_logic;
        i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
        i_wr_en:   IN  std_logic
    );
END ENTITY e_ram;

ARCHITECTURE a_ram OF e_ram IS

    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;

    SIGNAL s_buf: t_buf;

BEGIN

    p_ram: PROCESS(clk)
    BEGIN
        IF rising_edge(clk) THEN
            IF i_wr_en = '1' THEN
                s_buf(to_integer(unsigned(i_addr))) <= i_wr_data;
            END IF;
            o_rd_data <= s_buf(to_integer(unsigned(i_addr)));
        END IF;
    END PROCESS p_ram;

END ARCHITECTURE a_ram;