LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.textio.all;

ENTITY e_testbed IS
END ENTITY e_testbed;

ARCHITECTURE a_testbed OF e_testbed IS

    COMPONENT e_system IS
        PORT (
            rst:          IN  std_logic;
            clk:          IN  std_logic;
            pin_o_leds:   OUT std_logic_vector(7 DOWNTO 0)
        );
    END COMPONENT e_system;

    SIGNAL s_rst:    std_logic;
    SIGNAL s_clk:    std_logic;
    SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0);

BEGIN

    system: e_system
        PORT MAP (
            clk        => s_clk,
            rst        => s_rst,
            pin_o_leds => pin_leds
        );

    p_rst_clk: PROCESS
    BEGIN
        s_rst        <= '0';
        s_clk        <= '0';

        WAIT FOR 10 ns;
        s_rst <= '1';
        WAIT FOR 10 ns;
        s_rst <= '0';

        WHILE TRUE LOOP
            WAIT FOR 10 ns;
            s_clk <= '1';
            WAIT FOR 10 ns;
            s_clk <= '0';
        END LOOP;
    END PROCESS p_rst_clk;

END ARCHITECTURE a_testbed;