LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY e_io_eth IS
    PORT (
        rst:          IN  std_logic;
        clk:          IN  std_logic;
        i_addr:       IN  std_logic_vector( 1 DOWNTO 0);
        o_rd_data:    OUT std_logic_vector(31 DOWNTO 0);
        i_rd_en:      IN  std_logic_vector( 3 DOWNTO 0);
        i_wr_data:    IN  std_logic_vector(31 DOWNTO 0);
        i_wr_en:      IN  std_logic_vector( 3 DOWNTO 0);
        o_bm_req:     OUT std_logic;
        i_bm_grant:   IN  std_logic;
        o_bm_addr:    OUT std_logic_vector(31 DOWNTO 0);
        i_bm_rd_data: IN  std_logic_vector(31 DOWNTO 0);
        o_bm_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
        o_bm_wr_data: OUT std_logic_vector(31 DOWNTO 0);
        o_bm_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
        pin_o_nrst:   OUT std_logic;
        pin_i_rx_clk: IN  std_logic;
        pin_i_rxd:    IN  std_logic_vector(4 DOWNTO 0);
        pin_i_rx_dv:  IN  std_logic;
        pin_i_crs:    IN  std_logic;
        pin_i_col:    IN  std_logic;
        pin_i_tx_clk: IN  std_logic;
        pin_o_txd:    OUT std_logic_vector(3 DOWNTO 0);
        pin_o_tx_en:  OUT std_logic
    );
END ENTITY e_io_eth;

ARCHITECTURE a_io_eth OF e_io_eth IS

    SIGNAL s_rx_data:    std_logic_vector(7 DOWNTO 0);
    SIGNAL s_rx_data_en: std_logic;
    SIGNAL s_rx_done:    std_logic;
    SIGNAL s_rx_err:     std_logic;

    -- so far only for testing
    SIGNAL s_rx_fifo_wr_rdy:  std_logic;
    SIGNAL s_rx_fifo_wr_data: std_logic_vector(7 DOWNTO 0);
    SIGNAL s_rx_fifo_wr_en:   std_logic;
    SIGNAL s_rx_fifo_rd_rdy:  std_logic;
    SIGNAL s_rx_fifo_rd_data: std_logic_vector(7 DOWNTO 0);
    SIGNAL s_rx_fifo_rd_en:   std_logic;

    COMPONENT e_io_eth_rst IS
        PORT (
            rst:        IN  std_logic;
            clk:        IN  std_logic;
            pin_o_nrst: OUT std_logic
        );
    END COMPONENT e_io_eth_rst;

    COMPONENT e_io_eth_rxif IS
        PORT (
            rst:          IN  std_logic;
            clk:          IN  std_logic;
            o_data:       OUT std_logic_vector(7 DOWNTO 0);
            o_data_en:    OUT std_logic;
            o_done:       OUT std_logic;
            o_err:        OUT std_logic;
            pin_i_rx_clk: IN  std_logic;
            pin_i_rxd:    IN  std_logic_vector(4 DOWNTO 0);
            pin_i_rx_dv:  IN  std_logic;
            pin_i_crs:    IN  std_logic;
            pin_i_col:    IN  std_logic
        );
    END COMPONENT e_io_eth_rxif;

    -- so far only for testing
    COMPONENT e_block_fifo IS
        GENERIC (
            addr_width: natural;
            data_width: natural
        );
        PORT (
            rst:       IN  std_logic;
            clk:       IN  std_logic;
            o_wr_rdy:  OUT std_logic;
            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
            i_wr_en:   IN  std_logic;
            o_rd_rdy:  OUT std_logic;
            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
            i_rd_en:   IN  std_logic
        );
    END COMPONENT e_block_fifo;

    SIGNAL r_cnt: natural := 0;

BEGIN

    reset: e_io_eth_rst
        PORT MAP (
            rst        => rst,
            clk        => clk,
            pin_o_nrst => pin_o_nrst
        );

    rxif: e_io_eth_rxif
        PORT MAP (
            rst          => rst,
            clk          => clk,
            o_data       => s_rx_data,
            o_data_en    => s_rx_data_en,
            o_done       => s_rx_done,
            o_err        => s_rx_err,
            pin_i_rx_clk => pin_i_rx_clk,
            pin_i_rxd    => pin_i_rxd,
            pin_i_rx_dv  => pin_i_rx_dv,
            pin_i_crs    => pin_i_crs,
            pin_i_col    => pin_i_col
        );

    -- so far only for testing
    p_rx_if2fifo: PROCESS (s_rx_data, s_rx_data_en, s_rx_done, s_rx_err)
    BEGIN
        IF s_rx_err = '1' THEN
            s_rx_fifo_wr_data <= X"EE";
        ELSIF s_rx_done = '1' THEN
            s_rx_fifo_wr_data <= X"DD";
        ELSE
            s_rx_fifo_wr_data <= s_rx_data;
        END IF;
        s_rx_fifo_wr_en <= s_rx_data_en OR s_rx_done OR s_rx_err;
    END PROCESS p_rx_if2fifo;

    -- so far only for testing
    rx_fifo: e_block_fifo
        GENERIC MAP (
            addr_width => 11,
            data_width => 8
        )
        PORT MAP (
            rst       => rst,
            clk       => clk,
            o_wr_rdy  => s_rx_fifo_wr_rdy,
            i_wr_data => s_rx_fifo_wr_data,
            i_wr_en   => s_rx_fifo_wr_en,
            o_rd_rdy  => s_rx_fifo_rd_rdy,
            o_rd_data => s_rx_fifo_rd_data,
            i_rd_en   => s_rx_fifo_rd_en
        );

    -- so far only for testing
    s_rx_fifo_rd_en <= '1' WHEN i_addr = "01" AND i_rd_en(0) = '1' ELSE '0';

    -- so far only for testing
    p_rx_test_rd: PROCESS (rst, clk)
    BEGIN
        IF rst = '1' THEN
            o_rd_data       <= X"00000000";
        ELSIF rising_edge(clk) THEN
            o_rd_data       <= X"00000000";
            IF i_addr = "00" THEN
                o_rd_data(0) <= s_rx_fifo_rd_rdy;
            ELSIF i_addr = "01" THEN
                o_rd_data(7 DOWNTO 0) <= s_rx_fifo_rd_data;
            END IF;
        END IF;
    END PROCESS p_rx_test_rd;

    pin_o_txd   <= "0000";
    pin_o_tx_en <= '0';

    -- bus master: bullshit for now
    p_bm: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_cnt <= 0;
        ELSIF rising_edge(clk) THEN
            IF r_cnt < 3 THEN
                r_cnt <= r_cnt + 1;
            ELSE
                r_cnt <= 0;
            END IF;
        END IF;
    END PROCESS p_bm;

    -- bus master: bullshit for now
    o_bm_req     <= '1' WHEN r_cnt = 0 ELSE '0';
    o_bm_addr    <= (OTHERS => '0');
    o_bm_rd_en   <= (OTHERS => '0');
    o_bm_wr_data <= (OTHERS => '0');
    o_bm_wr_en   <= (OTHERS => '0');

END ARCHITECTURE a_io_eth;