https://git.blinkenarea.org/mips_sys/tree/f08af9fc9b59639677048e4f166c90f937ecffcf Recent commits to mips_sys (f08af9fc9b59639677048e4f166c90f937ecffcf) 2012-03-10T11:16:40+00:00 tag:gitlist.org,2012:commit/f08af9fc9b59639677048e4f166c90f937ecffcf remove unneeded type definition 2012-03-10T11:16:40+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/13632e3fb8b84f9ba839a2d899d399a135b678b7 fixed uninitialized / not resetted frame done output of ethernet TX frame processing 2012-03-10T10:56:08+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/1f34390a6202ad42a373516466fd9bb13fda11e2 added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing 2012-03-10T10:50:55+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/e5514ed21097063b2aee4d7a421e19118e4d59b0 send ethernet packet on center button press 2012-03-07T21:52:08+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/ee604bb9bf19f0780562dccfff9d84f3d2035e17 ethernet TX function takes const pointer 2012-03-07T21:19:40+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/de380fe29a5aed425f72210d28504be5a5cff963 adapt ethernet TX clock timing constraint to transmission of data on falling edge 2012-03-07T21:18:54+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/af62be09eb8ebe4defdd72f4595a375d6453d85c fix CRC generation during ethernet transmission trigger CRC generator only once per byte get CRC value _after_ last byte 2012-03-07T21:15:53+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/e31652feb71d8bfca42eaee64745c9e16db06946 transmit data on falling edge of ethernet TX clock 2012-03-07T21:15:19+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/6f152d956450f56af37807826b9c5f712700195b implemented ethernet RX packet and TX clock in testbed 2012-03-06T20:48:33+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt; tag:gitlist.org,2012:commit/230fe3b7e797cce9a8a42e7b8cca5d49eb381994 fixed FIFO implementation 2012-03-06T20:47:36+00:00 Stefan Schuermans stefan@schuermans.info <pre>&lt;/pre&gt;