implemented simple store instructions, preparations for load instructions (a29959d) - mips_sys · BlinkenArea

mips/core.vhd

@@ -8,7 +8,11 @@ ENTITY e_mips_core IS
         rst:            IN  std_logic;
         clk:            IN  std_logic;
         o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
-        i_instr_data: IN  std_logic_vector(31 DOWNTO 0)
+        i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
+        o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
+        i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
+        o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
+        o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
     );
 END ENTITY e_mips_core;
 
@@ -60,6 +64,10 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_reg_wr_en:   std_logic;
 
+    SIGNAL s_data_addr:     std_logic_vector(31 DOWNTO 0);
+    SIGNAL r_data_addr_dly: std_logic_vector(31 DOWNTO 0);
+    SIGNAL r_data_ldst_dly: t_ldst;
+
     COMPONENT e_mips_decoder IS
         PORT (
             i_instr:  IN  std_logic_vector(31 DOWNTO 0);
@@ -219,9 +227,7 @@ BEGIN
                 WHEN imm_16se =>
                     s_alu_op1 <= s_val_s;
                     s_alu_op2(15 DOWNTO 0) <= r_imm_16;
-                    IF (r_imm_16(15) = '1') THEN
-                        s_alu_op2(31 DOWNTO 16) <= (OTHERS => '1');
-                    END IF;
+                    s_alu_op2(31 DOWNTO 16) <= (OTHERS => r_imm_16(15));
                 WHEN imm_16ze =>
                     s_alu_op1 <= s_val_s;
                     s_alu_op2(15 DOWNTO 0) <= r_imm_16;
@@ -276,5 +282,76 @@ BEGIN
         END IF;
     END PROCESS p_next_pc;
 
-END ARCHITECTURE a_mips_core;
+    p_data_addr: PROCESS(r_op, s_val_s, r_imm_16)
+        VARIABLE v_ofs: signed(31 DOWNTO 0);
+        VARIABLE v_addr: signed(31 DOWNTO 0);
+    BEGIN
+        s_data_addr <= (OTHERS => '0');
+        IF r_op = op_l OR r_op = op_s THEN
+            v_ofs(15 DOWNTO 0)  := signed(r_imm_16);
+            v_ofs(31 DOWNTO 16) := (OTHERS => r_imm_16(15));
+            v_addr              := signed(s_val_s) + v_ofs;
+            s_data_addr         <= std_logic_vector(v_addr);
+        END IF;
+    END PROCESS p_data_addr;
+
+    o_data_addr <= s_data_addr(31 DOWNTO 2) & "00";
 
+    p_data_wr: PROCESS(r_op, r_ldst, s_data_addr, s_val_t)
+        VARIABLE v_ofs: signed(31 DOWNTO 0);
+        VARIABLE v_addr: signed(31 DOWNTO 0);
+    BEGIN
+        o_data_wr_data <= (OTHERS => '0');
+        o_data_wr_en   <= "0000";
+        IF r_op = op_s THEN
+            CASE r_ldst IS
+                WHEN ldst_b =>
+                    CASE s_data_addr(1 DOWNTO 0) IS
+                        WHEN "00" =>
+                            o_data_wr_data( 7 DOWNTO  0) <= s_val_t(7 DOWNTO 0);
+                            o_data_wr_en                 <= "0001";
+                        WHEN "01" =>
+                            o_data_wr_data(15 DOWNTO  8) <= s_val_t(7 DOWNTO 0);
+                            o_data_wr_en                 <= "0010";
+                        WHEN "10" =>
+                            o_data_wr_data(23 DOWNTO 16) <= s_val_t(7 DOWNTO 0);
+                            o_data_wr_en                 <= "0100";
+                        WHEN "11" =>
+                            o_data_wr_data(31 DOWNTO 24) <= s_val_t(7 DOWNTO 0);
+                            o_data_wr_en                 <= "1000";
+                        WHEN OTHERS => NULL;
+                    END CASE;
+                WHEN ldst_h =>
+                    CASE s_data_addr(1 DOWNTO 1) IS
+                        WHEN "0" =>
+                            o_data_wr_data(15 DOWNTO  0) <= s_val_t(15 DOWNTO 0);
+                            o_data_wr_en                 <= "0011";
+                        WHEN "1" =>
+                            o_data_wr_data(31 DOWNTO 16) <= s_val_t(15 DOWNTO 0);
+                            o_data_wr_en                 <= "1100";
+                        WHEN OTHERS => NULL;
+                    END CASE;
+                WHEN ldst_w =>
+                    o_data_wr_data <= s_val_t;
+                    o_data_wr_en   <= "1111";
+                WHEN OTHERS => NULL;
+            END CASE;
+        END IF;
+    END PROCESS p_data_wr;
+
+    p_data_rd_sync: PROCESS(rst, clk)
+    BEGIN
+        IF rst = '1' THEN
+            r_data_addr_dly <= (OTHERS => '0');
+            r_data_ldst_dly <= ldst_none;
+        ELSIF rising_edge(clk) THEN
+            r_data_addr_dly <= s_data_addr;
+            IF r_op = op_l THEN
+                r_data_ldst_dly <= r_ldst;
+            ELSE
+                r_data_ldst_dly <= ldst_none;
+            END IF;
+        END IF;
+    END PROCESS p_data_rd_sync;
+
+END ARCHITECTURE a_mips_core;


...	...	@@ -8,7 +8,11 @@ ENTITY e_mips_core IS
8	8	rst: IN std_logic;
9	9	clk: IN std_logic;
10	10	o_instr_addr: OUT std_logic_vector(31 DOWNTO 0);
11		- i_instr_data: IN std_logic_vector(31 DOWNTO 0)
	11	+ i_instr_data: IN std_logic_vector(31 DOWNTO 0);
	12	+ o_data_addr: OUT std_logic_vector(31 DOWNTO 0);
	13	+ i_data_rd_data: IN std_logic_vector(31 DOWNTO 0);
	14	+ o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
	15	+ o_data_wr_en: OUT std_logic_vector( 3 DOWNTO 0)
12	16	);
13	17	END ENTITY e_mips_core;
14	18
...	...	@@ -60,6 +64,10 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
60	64	SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);
61	65	SIGNAL s_reg_wr_en: std_logic;
62	66
	67	+ SIGNAL s_data_addr: std_logic_vector(31 DOWNTO 0);
	68	+ SIGNAL r_data_addr_dly: std_logic_vector(31 DOWNTO 0);
	69	+ SIGNAL r_data_ldst_dly: t_ldst;
	70	+
63	71	COMPONENT e_mips_decoder IS
64	72	PORT (
65	73	i_instr: IN std_logic_vector(31 DOWNTO 0);
...	...	@@ -219,9 +227,7 @@ BEGIN
219	227	WHEN imm_16se =>
220	228	s_alu_op1 <= s_val_s;
221	229	s_alu_op2(15 DOWNTO 0) <= r_imm_16;
222		- IF (r_imm_16(15) = '1') THEN
223		- s_alu_op2(31 DOWNTO 16) <= (OTHERS => '1');
224		- END IF;
	230	+ s_alu_op2(31 DOWNTO 16) <= (OTHERS => r_imm_16(15));
225	231	WHEN imm_16ze =>
226	232	s_alu_op1 <= s_val_s;
227	233	s_alu_op2(15 DOWNTO 0) <= r_imm_16;
...	...	@@ -276,5 +282,76 @@ BEGIN
276	282	END IF;
277	283	END PROCESS p_next_pc;
278	284
279		-END ARCHITECTURE a_mips_core;
	285	+ p_data_addr: PROCESS(r_op, s_val_s, r_imm_16)
	286	+ VARIABLE v_ofs: signed(31 DOWNTO 0);
	287	+ VARIABLE v_addr: signed(31 DOWNTO 0);
	288	+ BEGIN
	289	+ s_data_addr <= (OTHERS => '0');
	290	+ IF r_op = op_l OR r_op = op_s THEN
	291	+ v_ofs(15 DOWNTO 0) := signed(r_imm_16);
	292	+ v_ofs(31 DOWNTO 16) := (OTHERS => r_imm_16(15));
	293	+ v_addr := signed(s_val_s) + v_ofs;
	294	+ s_data_addr <= std_logic_vector(v_addr);
	295	+ END IF;
	296	+ END PROCESS p_data_addr;
	297	+
	298	+ o_data_addr <= s_data_addr(31 DOWNTO 2) & "00";
280	299
	300	+ p_data_wr: PROCESS(r_op, r_ldst, s_data_addr, s_val_t)
	301	+ VARIABLE v_ofs: signed(31 DOWNTO 0);
	302	+ VARIABLE v_addr: signed(31 DOWNTO 0);
	303	+ BEGIN
	304	+ o_data_wr_data <= (OTHERS => '0');
	305	+ o_data_wr_en <= "0000";
	306	+ IF r_op = op_s THEN
	307	+ CASE r_ldst IS
	308	+ WHEN ldst_b =>
	309	+ CASE s_data_addr(1 DOWNTO 0) IS
	310	+ WHEN "00" =>
	311	+ o_data_wr_data( 7 DOWNTO 0) <= s_val_t(7 DOWNTO 0);
	312	+ o_data_wr_en <= "0001";
	313	+ WHEN "01" =>
	314	+ o_data_wr_data(15 DOWNTO 8) <= s_val_t(7 DOWNTO 0);
	315	+ o_data_wr_en <= "0010";
	316	+ WHEN "10" =>
	317	+ o_data_wr_data(23 DOWNTO 16) <= s_val_t(7 DOWNTO 0);
	318	+ o_data_wr_en <= "0100";
	319	+ WHEN "11" =>
	320	+ o_data_wr_data(31 DOWNTO 24) <= s_val_t(7 DOWNTO 0);
	321	+ o_data_wr_en <= "1000";
	322	+ WHEN OTHERS => NULL;
	323	+ END CASE;
	324	+ WHEN ldst_h =>
	325	+ CASE s_data_addr(1 DOWNTO 1) IS
	326	+ WHEN "0" =>
	327	+ o_data_wr_data(15 DOWNTO 0) <= s_val_t(15 DOWNTO 0);
	328	+ o_data_wr_en <= "0011";
	329	+ WHEN "1" =>
	330	+ o_data_wr_data(31 DOWNTO 16) <= s_val_t(15 DOWNTO 0);
	331	+ o_data_wr_en <= "1100";
	332	+ WHEN OTHERS => NULL;
	333	+ END CASE;
	334	+ WHEN ldst_w =>
	335	+ o_data_wr_data <= s_val_t;
	336	+ o_data_wr_en <= "1111";
	337	+ WHEN OTHERS => NULL;
	338	+ END CASE;
	339	+ END IF;
	340	+ END PROCESS p_data_wr;
	341	+
	342	+ p_data_rd_sync: PROCESS(rst, clk)
	343	+ BEGIN
	344	+ IF rst = '1' THEN
	345	+ r_data_addr_dly <= (OTHERS => '0');
	346	+ r_data_ldst_dly <= ldst_none;
	347	+ ELSIF rising_edge(clk) THEN
	348	+ r_data_addr_dly <= s_data_addr;
	349	+ IF r_op = op_l THEN
	350	+ r_data_ldst_dly <= r_ldst;
	351	+ ELSE
	352	+ r_data_ldst_dly <= ldst_none;
	353	+ END IF;
	354	+ END IF;
	355	+ END PROCESS p_data_rd_sync;
	356	+
	357	+END ARCHITECTURE a_mips_core;
281	358