mips_sys

@@ -337,9 +337,10 @@ BEGIN

     o_data_addr <= s_data_addr(31 DOWNTO 2) & "00";

-    p_data_rd: PROCESS(r_data_rd, r_op, r_ldst, s_data_addr, r_reg_t, i_data_rd_data)

+    p_data_rd: PROCESS(r_data_rd, r_op, r_ldst, s_data_addr, r_reg_t, i_data_rd_data, s_val_t)

         VARIABLE v_b: std_logic_vector( 7 DOWNTO 0);

         VARIABLE v_h: std_logic_vector(15 DOWNTO 0);

+        VARIABLE v_w: std_logic_vector(31 DOWNTO 0);

     BEGIN

         s_stall_data_rd    <= '0';

         n_data_rd          <= data_rd_idle;

@@ -378,6 +379,26 @@ BEGIN

                         END IF;

                     WHEN ldst_w =>

                         s_reg_wr_data_data <= i_data_rd_data;

+                    WHEN ldst_wl =>

+                        v_w := s_val_t;

+                        CASE s_data_addr(1 DOWNTO 0) IS

+                            WHEN "00" => v_w(31 DOWNTO 24) := i_data_rd_data( 7 DOWNTO 0);

+                            WHEN "01" => v_w(31 DOWNTO 16) := i_data_rd_data(15 DOWNTO 0);

+                            WHEN "10" => v_w(31 DOWNTO  8) := i_data_rd_data(23 DOWNTO 0);

+                            WHEN "11" => v_w(31 DOWNTO  0) := i_data_rd_data(31 DOWNTO 0);

+                            WHEN OTHERS => NULL;

+                        END CASE;

+                        s_reg_wr_data_data <= v_w;

+                    WHEN ldst_wr =>

+                        v_w := s_val_t;

+                        CASE s_data_addr(1 DOWNTO 0) IS

+                            WHEN "00" => v_w(31 DOWNTO  0) := i_data_rd_data(31 DOWNTO  0);

+                            WHEN "01" => v_w(23 DOWNTO  0) := i_data_rd_data(31 DOWNTO  8);

+                            WHEN "10" => v_w(15 DOWNTO  0) := i_data_rd_data(31 DOWNTO 16);

+                            WHEN "11" => v_w( 7 DOWNTO  0) := i_data_rd_data(31 DOWNTO 24);

+                            WHEN OTHERS => NULL;

+                        END CASE;

+                        s_reg_wr_data_data <= v_w;

                     WHEN OTHERS => NULL;

                 END CASE;

                 s_reg_wr_data_no <= r_reg_t;