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0a29d2e
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mips_sys
mips_sys.xise
separated shifter from ALU
Stefan Schuermans
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0a29d2e
at 2012-01-24 20:43:21
mips_sys.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> <header> <!-- ISE source project file created by Project Navigator. --> <!-- --> <!-- This file contains project source information including a list of --> <!-- project source files, project and process properties. This file, --> <!-- along with the project source files, is sufficient to open and --> <!-- implement in ISE Project Navigator. --> <!-- --> <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> </header> <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> <files> <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" 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xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/> <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> <property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-23T20:57:37" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="504447C81FC3113F3078F816935626AA" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> </properties> <bindings> <binding xil_pn:location="/e_mips_core" xil_pn:name="constraints/clk.ucf"/> <binding xil_pn:location="/e_mips_core" xil_pn:name="constraints/rst.ucf"/> </bindings> <libraries/> <autoManagedFiles> <!-- The following files are identified by `include statements in verilog --> <!-- source files and are automatically managed by Project Navigator. --> <!-- --> <!-- Do not hand-edit this section, as it will be overwritten when the --> <!-- project is analyzed based on files automatically identified as --> <!-- include files. --> </autoManagedFiles> </project>
