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0e00df4
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master
mips_sys
fw
ram.pl
implemented loading of data memory from firmware
Stefan Schuermans
commited
0e00df4
at 2012-02-12 17:47:50
ram.pl
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#! /usr/bin/perl use strict; use warnings; if (@ARGV < 2) { die "usage: $0 <binary file> <ram number>\n"; } my $binfile = $ARGV[0]; my $ramno = abs(int($ARGV[1])); open BINFILE, "<", $binfile or die "cannot read \"$binfile\": "; binmode BINFILE; print <<EOF; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY e_ram_$ramno IS GENERIC ( addr_width: natural ); PORT ( clk: IN std_logic; i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0); o_rd_data: OUT std_logic_vector( 7 DOWNTO 0); i_wr_data: IN std_logic_vector( 7 DOWNTO 0); i_wr_en: IN std_logic ); END ENTITY e_ram_$ramno; ARCHITECTURE a_ram_$ramno OF e_ram_$ramno IS SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0); SUBTYPE t_data IS std_logic_vector( 7 DOWNTO 0); TYPE t_buf IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data; SIGNAL s_buf: t_buf := ( EOF my $addr = 0; my $data; while (read(BINFILE, $data, 4)) { my @d = unpack("CCCC", $data); printf " %d => X\"%02X\",\n", $addr, $d[$ramno]; ++$addr; } print <<EOF; OTHERS => X"00" ); BEGIN p_ram: PROCESS(clk) BEGIN IF rising_edge(clk) THEN IF i_wr_en = '1' THEN s_buf(to_integer(unsigned(i_addr))) <= i_wr_data; END IF; o_rd_data <= s_buf(to_integer(unsigned(i_addr))); END IF; END PROCESS p_ram; END ARCHITECTURE a_ram_$ramno; EOF close BINFILE;