mips/alu.vhd (ee91dd2) - mips_sys · BlinkenArea

alu.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;

ENTITY e_mips_alu IS
    PORT (
        i_alu: IN  t_alu;
        i_op1: IN  std_logic_vector(31 DOWNTO 0);
        i_op2: IN  std_logic_vector(31 DOWNTO 0);
        o_res: OUT std_logic_vector(31 DOWNTO 0)
    );
END ENTITY e_mips_alu;

ARCHITECTURE a_mips_alu OF e_mips_alu IS

BEGIN

p_alu: PROCESS(i_alu, i_op1, i_op2)
        VARIABLE v_op1_s: signed(31 DOWNTO 0);
        VARIABLE v_op2_s: signed(31 DOWNTO 0);
        VARIABLE v_op1_u: unsigned(31 DOWNTO 0);
        VARIABLE v_op2_u: unsigned(31 DOWNTO 0);
        VARIABLE v_int5:  integer RANGE 31 DOWNTO 0;
        VARIABLE v_tmp64: std_logic_vector(63 DOWNTO 0);
    BEGIN
        v_op1_s := signed(i_op1);
        v_op2_s := signed(i_op2);
        v_op1_u := unsigned(i_op1);
        v_op2_u := unsigned(i_op2);
        CASE i_alu IS
            WHEN alu_add => o_res <= std_logic_vector(v_op1_s + v_op2_s);
            WHEN alu_and => o_res <= i_op1 AND i_op2;
            WHEN alu_nor => o_res <= i_op1 NOR i_op2;
            WHEN alu_or  => o_res <= i_op1 OR i_op2;
            WHEN alu_sub => o_res <= std_logic_vector(v_op1_s - v_op2_s);
            WHEN alu_sll => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
                                v_tmp64 := i_op1 & X"00000000";
                                o_res   <= v_tmp64(v_int5 + 31 DOWNTO v_int5);
                            ELSE
                                o_res   <= X"00000000";
                            END IF;
            WHEN alu_sra => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
                                IF i_op1(31) = '1' THEN
                                    v_tmp64 := X"FFFFFFFF" & i_op1;
                                ELSE
                                    v_tmp64 := X"00000000" & i_op1;
                                END IF;
                                o_res   <= v_tmp64(63 - v_int5 DOWNTO 32 - v_int5);
                            ELSE
                                o_res   <= X"00000000";
                            END IF;
            WHEN alu_srl => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
                                v_tmp64 := X"00000000" & i_op1;
                                o_res   <= v_tmp64(63 - v_int5 DOWNTO 32 - v_int5);
                            ELSE
                                o_res   <= X"00000000";
                            END IF;
            WHEN alu_slt => IF v_op1_s < v_op2_s THEN
                                o_res <= X"00000001";
                            ELSE
                                o_res <= X"00000000";
                            END IF;
            WHEN alu_xor => o_res <= i_op1 XOR i_op2;
            WHEN OTHERS => o_res <= X"00000000";
        END CASE;
    END PROCESS p_alu;

END ARCHITECTURE a_mips_alu;

mips_sys

start of MIPS core: begin of decoder and ALU