blocks/rwram_dc.vhd (1f34390) - mips_sys · BlinkenArea

rwram_dc.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

-- read write RAM with dual clocks

ENTITY e_block_rwram_dc IS
    GENERIC (
        addr_width: natural;
        data_width: natural
    );
    PORT (
        rd_clk:    IN  std_logic;
        i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
        wr_clk:    IN  std_logic;
        i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
        i_wr_en:   IN  std_logic
    );
END ENTITY e_block_rwram_dc;

ARCHITECTURE a_block_rwram_dc OF e_block_rwram_dc IS

SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;

SIGNAL s_buf: t_buf;

BEGIN

p_rd: PROCESS(rd_clk)
    BEGIN
        IF rising_edge(rd_clk) THEN
            o_rd_data <= s_buf(to_integer(unsigned(i_rd_addr)));
        END IF;
    END PROCESS p_rd;

p_wr: PROCESS(wr_clk)
    BEGIN
        IF rising_edge(wr_clk) THEN
            IF i_wr_en = '1' THEN
                s_buf(to_integer(unsigned(i_wr_addr))) <= i_wr_data;
            END IF;
        END IF;
    END PROCESS p_wr;

END ARCHITECTURE a_block_rwram_dc;

mips_sys

added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing