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70d97c2
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master
mips_sys
mips_sys.xise
migration to Xilinx 13.4
Stefan Schuermans
commited
70d97c2
at 2012-03-24 14:06:11
mips_sys.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> <header> <!-- ISE source project file created by Project Navigator. --> <!-- --> <!-- This file contains project source information including a list of --> <!-- project source files, project and process properties. This file, --> <!-- along with the project source files, is sufficient to open and --> <!-- implement in ISE Project Navigator. --> <!-- --> <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> </header> <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> <files> <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/> </file> <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/> </file> <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/> </file> <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/> </file> <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> <association xil_pn:name="Implementation" xil_pn:seqID="33"/> </file> <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/> </file> <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/> </file> <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/> </file> <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/> </file> <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/> </file> <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/> </file> <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/> <association xil_pn:name="Implementation" xil_pn:seqID="32"/> </file> <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/> </file> <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> <association xil_pn:name="Implementation" xil_pn:seqID="30"/> </file> <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/> </file> <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/> </file> <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> <association 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xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/> <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" 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xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> <property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="iMPACT Project File" xil_pn:value="mips_sys.ipf" xil_pn:valueState="non-default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|e_testbed|a_testbed" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-23T20:57:37" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="504447C81FC3113F3078F816935626AA" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> </properties> <bindings> <binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/lcd.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/switches.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/uart.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/eth.ucf"/> </bindings> <libraries/> <autoManagedFiles> <!-- The following files are identified by `include statements in verilog --> <!-- source files and are automatically managed by Project Navigator. --> <!-- --> <!-- Do not hand-edit this section, as it will be overwritten when the --> <!-- project is analyzed based on files automatically identified as --> <!-- include files. --> </autoManagedFiles> </project>
