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47f05ce
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mips_sys
io
eth
rst.vhd
begin of ethernet RX implementation, so far only test interface to core, does not meet timing
Stefan Schuermans
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47f05ce
at 2012-02-20 21:16:03
rst.vhd
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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY e_io_eth_rst IS PORT ( rst: IN std_logic; clk: IN std_logic; pin_o_nrst: OUT std_logic ); END ENTITY e_io_eth_rst; ARCHITECTURE a_io_eth_rst OF e_io_eth_rst IS CONSTANT c_rst_dur: natural := 5000; SIGNAL r_rst_cnt: natural RANGE 0 TO c_rst_dur - 1 := 0; SIGNAL r_nrst: std_logic := '0'; BEGIN p_rst: PROCESS(rst, clk) BEGIN IF rst = '1' THEN r_rst_cnt <= 0; r_nrst <= '0'; ELSIF rising_edge(clk) THEN IF r_rst_cnt = c_rst_dur - 1 THEN r_nrst <= '1'; ELSE r_rst_cnt <= r_rst_cnt + 1; END IF; END IF; END PROCESS p_rst; pin_o_nrst <= r_nrst; END ARCHITECTURE a_io_eth_rst;
