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a086ce1
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mips_sys
mips_sys.xise
clock and reset constraints are for whole system
Stefan Schuermans
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a086ce1
at 2012-02-10 23:22:30
mips_sys.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> <header> <!-- ISE source project file created by Project Navigator. --> <!-- --> <!-- This file contains project source information including a list of --> <!-- project source files, project and process properties. This file, --> <!-- along with the project source files, is sufficient to open and --> <!-- implement in ISE Project Navigator. --> <!-- --> <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> </header> <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> <files> <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/> </file> <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> <file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/> </file> <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/> </file> <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/> </file> <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/> </file> <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="159"/> </file> <file xil_pn:name="constraints/rst.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="160"/> </file> </files> <properties> <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow Unmatched Timing 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xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="e_system" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> 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<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 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internal use only. These should not be modified.--> <!-- --> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|e_testbed|a_testbed" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-23T20:57:37" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="504447C81FC3113F3078F816935626AA" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> </properties> <bindings> <binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/> <binding xil_pn:location="/e_system" xil_pn:name="constraints/rst.ucf"/> </bindings> <libraries/> <autoManagedFiles> <!-- The following files are identified by `include statements in verilog --> <!-- source files and are automatically managed by Project Navigator. --> <!-- --> <!-- Do not hand-edit this section, as it will be overwritten when the --> <!-- project is analyzed based on files automatically identified as --> <!-- include files. --> </autoManagedFiles> </project>
