io/switches.vhd (5e29ab5) - mips_sys · BlinkenArea

switches.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.io_switches_pins.all;

ENTITY e_io_switches IS
    PORT (
        rst:            IN  std_logic;
        clk:            IN  std_logic;
        i_addr:         IN  std_logic_vector( 0 DOWNTO 0);
        o_rd_data:      OUT std_logic_vector(31 DOWNTO 0);
        pin_i_switches: IN  t_io_switches_pins
    );
END ENTITY e_io_switches;

ARCHITECTURE a_io_switches OF e_io_switches IS

SIGNAL n_sample: std_logic_vector(1 DOWNTO 0);
    SIGNAL r_sample: std_logic_vector(1 DOWNTO 0)  := (OTHERS => '0');
    SIGNAL r_prev:   std_logic_vector(1 DOWNTO 0)  := (OTHERS => '0');
    SIGNAL n_cnt:    std_logic_vector(31 DOWNTO 0);
    SIGNAL r_cnt:    std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');

BEGIN

p_sample: PROCESS(pin_i_switches)
    BEGIN
        -- de-gray-code rotary inputs
        IF pin_i_switches.rot_b = '1' THEN
            IF pin_i_switches.rot_a = '1' THEN
                n_sample <= "10";
            ELSE
                n_sample <= "11";
            END IF;
        ELSE
            IF pin_i_switches.rot_a = '1' THEN
                n_sample <= "01";
            ELSE
                n_sample <= "00";
            END IF;
        END IF;
    END PROCESS p_sample;

p_cnt: PROCESS(r_sample, r_prev, r_cnt)
        VARIABLE v_delta: signed(1 DOWNTO 0);
    BEGIN
        v_delta := signed(r_sample) - signed(r_prev);
        n_cnt <= std_logic_vector(signed(r_cnt) + v_delta);
    END PROCESS p_cnt;

p_sync: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_sample <= (OTHERS => '0');
            r_prev   <= (OTHERS => '0');
            r_cnt    <= (OTHERS => '0');
        ELSIF rising_edge(clk) THEN
            r_sample <= n_sample;
            r_prev   <= r_sample;
            r_cnt    <= n_cnt;
        END IF;
    END PROCESS p_sync;

p_read: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            o_rd_data <= (OTHERS => '0');
        ELSIF rising_edge(clk) THEN
            IF i_addr = "0" THEN
                o_rd_data( 3 DOWNTO  0) <= pin_i_switches.sw;
                o_rd_data( 7 DOWNTO  4) <= (OTHERS => '0');
                o_rd_data( 8)           <= pin_i_switches.east;
                o_rd_data( 9)           <= pin_i_switches.north;
                o_rd_data(10)           <= pin_i_switches.south;
                o_rd_data(11)           <= pin_i_switches.west;
                o_rd_data(15 DOWNTO 12) <= (OTHERS => '0');
                o_rd_data(16)           <= pin_i_switches.center;
                o_rd_data(23 DOWNTO 17) <= (OTHERS => '0');
                o_rd_data(24)           <= pin_i_switches.rot_a;
                o_rd_data(25)           <= pin_i_switches.rot_b;
                o_rd_data(31 DOWNTO 26) <= (OTHERS => '0');
            ELSE
                o_rd_data <= r_cnt;
            END IF;
        END IF;
    END PROCESS p_read;

END ARCHITECTURE a_io_switches;

mips_sys

implemented switches