begin of ethernet RX implem...
Stefan Schuermans authored 12 years ago
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1) LIBRARY IEEE;
2) USE IEEE.STD_LOGIC_1164.ALL;
3) USE IEEE.NUMERIC_STD.ALL;
4)
5) ENTITY e_io_eth_rxif IS
6) PORT (
7) rst: IN std_logic;
8) clk: IN std_logic;
9) o_data: OUT std_logic_vector(7 DOWNTO 0);
10) o_data_en: OUT std_logic;
11) o_done: OUT std_logic;
12) o_err: OUT std_logic;
13) pin_i_rx_clk: IN std_logic;
14) pin_i_rxd: IN std_logic_vector(4 DOWNTO 0);
15) pin_i_rx_dv: IN std_logic;
16) pin_i_crs: IN std_logic;
17) pin_i_col: IN std_logic
18) );
19) END ENTITY e_io_eth_rxif;
20)
21) ARCHITECTURE a_io_eth_rxif OF e_io_eth_rxif IS
22)
23) TYPE t_in_state IS (in_idle, in_nibble, in_data, in_pre_done, in_done,
24) in_pre_err, in_err, in_post_err);
25)
26) SIGNAL r_in_state: t_in_state := in_idle;
27) SIGNAL r_in_data: std_logic_vector(7 DOWNTO 0) := X"00";
28)
29) TYPE t_if_event IS (if_data, if_done, if_err);
30)
31) SIGNAL r_if_rx_clk_trigger: std_logic := '0';
32) SIGNAL r_if_rx_clk_event: t_if_event := if_data;
33) SIGNAL r_if_rx_clk_data: std_logic_vector(7 DOWNTO 0) := X"00";
34)
35) SIGNAL r_if_clk_trigger: std_logic := '0';
36) SIGNAL r_if_clk_event: t_if_event := if_data;
37) SIGNAL r_if_clk_data: std_logic_vector(7 DOWNTO 0) := X"00";
38) SIGNAL r_if_clk_en: std_logic := '0';
39)
40) SIGNAL r_out_data: std_logic_vector(7 DOWNTO 0) := X"00";
41) SIGNAL r_out_data_en: std_logic := '0';
42) SIGNAL r_out_done: std_logic := '0';
43) SIGNAL r_out_err: std_logic := '0';
44)
45) BEGIN
46)
47) p_in: PROCESS(rst, pin_i_rx_clk)
48) BEGIN
49) IF rst = '1' THEN
50) r_in_state <= in_idle;
51) r_in_data <= X"00";
52) ELSIF rising_edge(pin_i_rx_clk) THEN
53) CASE r_in_state IS
54) WHEN in_idle =>
55) IF pin_i_col = '1' THEN
56) r_in_state <= in_pre_err;
57) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN
58) IF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err
59) r_in_state <= in_pre_err;
60) ELSE
61) r_in_state <= in_nibble;
62) r_in_data(3 DOWNTO 0) <= pin_i_rxd(3 DOWNTO 0);
63) END IF;
64) END IF;
65) WHEN in_nibble =>
66) IF pin_i_col = '1' THEN
67) r_in_state <= in_err;
68) ELSIF pin_i_crs = '0' OR pin_i_rx_dv = '0' THEN
69) r_in_state <= in_err;
70) ELSIF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err
71) r_in_state <= in_err;
72) ELSE
73) r_in_state <= in_data;
74) r_in_data(7 DOWNTO 4) <= pin_i_rxd(3 DOWNTO 0);
75) END IF;
76) WHEN in_data =>
77) IF pin_i_col = '1' THEN
78) r_in_state <= in_pre_err;
79) ELSIF pin_i_crs = '0' OR pin_i_rx_dv = '0' THEN
80) r_in_state <= in_pre_done;
81) ELSIF pin_i_rxd(4) = '1' THEN -- rxd(4) is rx_err
82) r_in_state <= in_pre_err;
83) ELSE
84) r_in_state <= in_nibble;
85) r_in_data(3 DOWNTO 0) <= pin_i_rxd(3 DOWNTO 0);
86) END IF;
87) WHEN in_pre_done =>
88) IF pin_i_col = '1' THEN
89) r_in_state <= in_err;
90) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN
91) r_in_state <= in_err;
92) ELSE
93) r_in_state <= in_done;
94) END IF;
95) WHEN in_done =>
96) IF pin_i_col = '1' THEN
97) r_in_state <= in_pre_err;
98) ELSIF pin_i_crs = '1' AND pin_i_rx_dv = '1' THEN
99) r_in_state <= in_err;
100) ELSE
101) r_in_state <= in_idle;
102) END IF;
103) WHEN in_pre_err =>
104) r_in_state <= in_err;
105) WHEN in_err =>
106) r_in_state <= in_post_err;
107) WHEN in_post_err =>
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begin of ethernet RX implem...