MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
improve 200ms tick and task processing, get rid of UART output of received ethernet frames
e5fcec6 @ 2012-03-24 19:05:42
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| testbed.vhd | improve 200ms tick and task processing, get rid of UART output of received ethernet frames | 2012-03-24 19:05:42 |