MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
added debug output functions
6360daf @ 2012-04-05 21:31:40
| .. | ||
|---|---|---|
| testbed.vhd | improve 200ms tick and task processing, get rid of UART output of received ethernet frames | 2012-03-24 19:05:42 |