MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
fixed srl instruction (no sign extension!)
293f304 @ 2012-04-05 21:32:02
| .. | ||
|---|---|---|
| alu.vhd | fixed srl instruction (no sign extension!) | 2012-04-05 21:32:02 |
| cmp.vhd | if not comparing, jump is unconditional, so compare must return true | 2012-02-10 22:45:59 |
| core.vhd | converted core to use req and grant signals to access data bus | 2012-03-01 21:23:47 |
| decoder.vhd | fixed decoding of M[FT]{HI|LO} | 2012-03-13 21:11:43 |
| div.vhd | fix divider (result) | 2012-03-21 22:11:20 |
| mul_fast.vhd | add initial values for registers | 2012-02-12 18:05:38 |
| mul_slow.vhd | add initial values for registers | 2012-02-12 18:05:38 |
| regs.vhd | add initial values for registers | 2012-02-12 18:05:38 |
| shifter.vhd | fix unused signals | 2012-02-05 13:21:27 |
| types.vhd | decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete | 2012-02-05 17:32:53 |