MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing
1f34390 @ 2012-03-10 10:50:55
| .. | ||
|---|---|---|
| system.vhd | implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) | 2012-03-05 22:01:56 |