MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
implemented multi-master feature for data bus extended ethernet block to have busmaster signals (dummy functionality up to now)
12f75e0 @ 2012-03-01 21:24:14
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| system.vhd | implemented multi-master feature for data bus extended ethernet block to have busmaster signals (dummy functionality up to now) | 2012-03-01 21:24:14 |